1//Original:/proj/frio/dv/testcases/core/c_seq_ex2_brcc_mp_mv_pop/c_seq_ex2_brcc_mp_mv_pop.dsp
2// Spec Reference: sequencer stage ex2  ( brcc (mis-pred)+ regmv + pushpopmultiple)
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(std.inc)
11include(selfcheck.inc)
12include(gen_int.inc)
13INIT_R_REGS(0);
14INIT_P_REGS(0);
15INIT_I_REGS(0);     // initialize the dsp address regs
16INIT_M_REGS(0);
17INIT_L_REGS(0);
18INIT_B_REGS(0);
19//CHECK_INIT(p5, 0xe0000000);
20include(symtable.inc)
21CHECK_INIT_DEF(p5);
22
23#ifndef STACKSIZE
24#define STACKSIZE 0x10
25#endif
26#ifndef EVT
27#define EVT  0xFFE02000
28#endif
29#ifndef EVT15
30#define EVT15  0xFFE0203C
31#endif
32#ifndef EVT_OVERRIDE
33#define EVT_OVERRIDE 0xFFE02100
34#endif
35#ifndef ITABLE
36#define ITABLE DATA_ADDR_1
37#endif
38
39GEN_INT_INIT(ITABLE) // set location for interrupt table
40
41//
42// Reset/Bootstrap Code
43//   (Here we should set the processor operating modes, initialize registers,
44//
45
46BOOT:
47
48                              // in reset mode now
49LD32_LABEL(sp, KSTACK);   // setup the stack pointer
50FP = SP;        // and frame pointer
51
52LD32(p0, EVT);      // Setup Event Vectors and Handlers
53LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
54    [ P0 ++ ] = R0;
55
56LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
57    [ P0 ++ ] = R0;
58
59LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
60    [ P0 ++ ] = R0;
61
62LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
63    [ P0 ++ ] = R0;
64
65    [ P0 ++ ] = R0;        // IVT4 not used
66
67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
68    [ P0 ++ ] = R0;
69
70LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
71    [ P0 ++ ] = R0;
72
73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
74    [ P0 ++ ] = R0;
75
76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
77    [ P0 ++ ] = R0;
78
79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
80    [ P0 ++ ] = R0;
81
82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
83    [ P0 ++ ] = R0;
84
85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
86    [ P0 ++ ] = R0;
87
88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
89    [ P0 ++ ] = R0;
90
91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
92    [ P0 ++ ] = R0;
93
94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
95    [ P0 ++ ] = R0;
96
97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
98    [ P0 ++ ] = R0;
99
100LD32(p0, EVT_OVERRIDE);
101    R0 = 0;
102    [ P0 ++ ] = R0;
103    R0 = -1;     // Change this to mask interrupts (*)
104    [ P0 ] = R0;   // IMASK
105CSYNC;
106
107DUMMY:
108
109    R0 = 0 (Z);
110
111LT0 = r0;       // set loop counters to something deterministic
112LB0 = r0;
113LC0 = r0;
114LT1 = r0;
115LB1 = r0;
116LC1 = r0;
117
118ASTAT = r0;     // reset other internal regs
119
120// The following code sets up the test for running in USER mode
121
122LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
123                        // ReturnFromInterrupt (RTI)
124RETI = r0;      // We need to load the return address
125
126// Comment the following line for a USER Mode test
127
128JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
129
130RTI;
131
132STARTSUP:
133LD32_LABEL(p1, BEGIN);
134
135LD32(p0, EVT15);
136    [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
137
138RAISE 15;   // after we RTI, INT 15 should be taken,& return to BEGIN in
139                // SUPERVISOR MODE & go to different RAISE in supervisor mode
140                // until the end of the test.
141
142NOP;    // Workaround for Bug 217
143RTI;
144
145//
146// The Main Program
147//
148STARTUSER:
149LD32_LABEL(sp, USTACK);   // setup the stack pointer
150FP = SP;            // set frame pointer
151JUMP BEGIN;
152
153//*********************************************************************
154
155BEGIN:
156
157                // COMMENT the following line for USER MODE tests
158    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
159
160                // **** YOUR CODE GOES HERE ****
161
162
163
164    // PUT YOUR TEST HERE!
165R0 = 0;
166ASTAT = R0;
167        R0 = 0x01;
168        R1 = 0x02;
169        R2 = 0x03;
170        R3 = 0x04;
171        R4 = 0x05;
172        R5 = 0x06;
173        R6 = 0x07;
174        R7 = 0x08;
175LD32(p1, 0x12345678);
176LD32(p2, 0x05612496);
177LD32(p3, 0xab5fd490);
178LD32(p4, 0xa581bd94);
179
180
181        [ -- SP ] = ( R7:0 );
182//  RAISE 2;    // RTN
183IF CC JUMP LABEL1 (BP);
184    P1 = R1;
185    R2 = P1;
186        [ -- SP ] = ( R7:0 );
187        R1 = 0x12;
188        R2 = 0x13;
189        R3 = 0x14;
190        R4 = 0x15;
191        R5 = 0x16;
192        R6 = 0x17;
193        R7 = 0x18;
194
195LABEL1:
196//  RAISE 5;    // RTI
197    P2 = R2;
198    R3 = P2;
199
200        [ -- SP ] = ( R7:0 );
201
202        R2 = 0x23;
203        R3 = 0x24;
204        R4 = 0x25;
205        R5 = 0x26;
206        R6 = 0x27;
207        R7 = 0x28;
208
209//  RAISE 6;    // RTI
210IF !CC JUMP LABEL2 (BP);
211    P3 = R3;
212    R4 = P3;
213        [ -- SP ] = ( R7:0 );
214// POP
215        R0 = 0x00;
216        R1 = 0x00;
217        R2 = 0x00;
218        R3 = 0x00;
219        R4 = 0x00;
220        R5 = 0x00;
221        R6 = 0x00;
222        R7 = 0x00;
223
224LABEL2:
225//  RAISE 7;    // RTI
226IF CC JUMP LABEL4 (BP);             // SHOULD NOT EXECUTE
227    P4 = R4;
228    R5 = P4;
229        ( R7:0 ) = [ SP ++ ];
230
231LABEL4:
232
233CHECKREG(r0, 0x00000001);
234CHECKREG(r1, 0x00000012);
235CHECKREG(r2, 0x00000013);
236CHECKREG(r3, 0x00000013);
237CHECKREG(r4, 0x00000015);
238CHECKREG(r5, 0x00000016);
239CHECKREG(r6, 0x00000017);
240CHECKREG(r7, 0x00000018);
241
242//  RAISE 8;    // RTI
243IF !CC JUMP LABEL3 (BP);
244    P1 = R5;
245    R6 = P1;
246        ( R7:0 ) = [ SP ++ ];
247//CHECKREG(r0, 0x000000a1);  // CHECKREG can not be skipped
248//CHECKREG(r1, 0x000000b2);  // so they cannot appear here
249//CHECKREG(r2, 0x000000c3);
250//CHECKREG(r3, 0x000000d4);
251//CHECKREG(r4, 0x000000e5);
252//CHECKREG(r5, 0x000000f6);
253//CHECKREG(r6, 0x00000017);
254//CHECKREG(r7, 0x00000028);
255   R0 = 12;
256   R1 = 13;
257   R2 = 14;
258   R3 = 15;
259   R4 = 16;
260   R5 = 17;
261   R6 = 18;
262   R7 = 19;
263
264
265LABEL3:
266//  RAISE 9;    // RTI
267    P2 = R6;
268    R7 = P2;
269        ( R7:0 ) = [ SP ++ ];
270
271CHECKREG(r0, 0x00000001);
272CHECKREG(r1, 0x00000002);
273CHECKREG(r2, 0x00000002);
274CHECKREG(r3, 0x00000004);
275CHECKREG(r4, 0x00000005);
276CHECKREG(r5, 0x00000006);
277CHECKREG(r6, 0x00000007);
278CHECKREG(r7, 0x00000008);
279R0 = I0;
280R1 = I1;
281R2 = I2;
282R3 = I3;
283CHECKREG(r0, 0x00000000);
284CHECKREG(r1, 0x00000000);
285CHECKREG(r2, 0x00000000);
286CHECKREG(r3, 0x00000000);
287
288
289END:
290dbg_pass;            // End the test
291
292//*********************************************************************
293
294//
295// Handlers for Events
296//
297
298EHANDLE:            // Emulation Handler 0
299RTE;
300
301RHANDLE:            // Reset Handler 1
302RTI;
303
304NHANDLE:            // NMI Handler 2
305    I0 += 2;
306RTN;
307
308XHANDLE:            // Exception Handler 3
309    R1 = 3;
310RTX;
311
312HWHANDLE:           // HW Error Handler 5
313    I1 += 2;
314RTI;
315
316THANDLE:            // Timer Handler 6
317    I2 += 2;
318RTI;
319
320I7HANDLE:           // IVG 7 Handler
321    I3 += 2;
322RTI;
323
324I8HANDLE:           // IVG 8 Handler
325    I0 += 2;
326RTI;
327
328I9HANDLE:           // IVG 9 Handler
329    I0 += 2;
330RTI;
331
332I10HANDLE:          // IVG 10 Handler
333    R7 = 10;
334RTI;
335
336I11HANDLE:          // IVG 11 Handler
337    I0 = R0;
338    I1 = R1;
339    I2 = R2;
340    I3 = R3;
341    M0 = R4;
342    R0 = 11;
343RTI;
344
345I12HANDLE:          // IVG 12 Handler
346    R1 = 12;
347RTI;
348
349I13HANDLE:          // IVG 13 Handler
350    R2 = 13;
351RTI;
352
353I14HANDLE:          // IVG 14 Handler
354    R3 = 14;
355RTI;
356
357I15HANDLE:          // IVG 15 Handler
358    R4 = 15;
359RTI;
360
361NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
362
363//
364// Data Segment
365//
366
367.data
368DATA:
369    .space (0x10);
370
371// Stack Segments (Both Kernel and User)
372
373    .space (STACKSIZE);
374KSTACK:
375
376    .space (STACKSIZE);
377USTACK:
378