1//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmr_mvp/c_seq_ex3_ls_mmr_mvp.dsp 2// Spec Reference: sequencer stage ex3 (ldst + mmr regmv + pushpopmultiple) 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(std.inc) 11include(selfcheck.inc) 12include(gen_int.inc) 13INIT_R_REGS(0); 14INIT_P_REGS(0); 15INIT_I_REGS(0); // initialize the dsp address regs 16INIT_M_REGS(0); 17INIT_L_REGS(0); 18INIT_B_REGS(0); 19//CHECK_INIT(p5, 0xe0000000); 20include(symtable.inc) 21CHECK_INIT_DEF(p5); 22 23#ifndef STACKSIZE 24#define STACKSIZE 0x10 25#endif 26#ifndef EVT 27#define EVT 0xFFE02000 28#endif 29#ifndef EVT15 30#define EVT15 0xFFE0203C 31#endif 32#ifndef EVT_OVERRIDE 33#define EVT_OVERRIDE 0xFFE02100 34#endif 35#ifndef ITABLE 36#define ITABLE DATA_ADDR_1 37#endif 38 39GEN_INT_INIT(ITABLE) // set location for interrupt table 40 41// 42// Reset/Bootstrap Code 43// (Here we should set the processor operating modes, initialize registers, 44// 45 46BOOT: 47 48 // in reset mode now 49LD32_LABEL(sp, KSTACK); // setup the stack pointer 50FP = SP; // and frame pointer 51 52LD32(p0, EVT); // Setup Event Vectors and Handlers 53LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 54 [ P0 ++ ] = R0; 55 56LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 57 [ P0 ++ ] = R0; 58 59LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 60 [ P0 ++ ] = R0; 61 62LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 63 [ P0 ++ ] = R0; 64 65 [ P0 ++ ] = R0; // IVT4 not used 66 67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 68 [ P0 ++ ] = R0; 69 70LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 71 [ P0 ++ ] = R0; 72 73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 74 [ P0 ++ ] = R0; 75 76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 77 [ P0 ++ ] = R0; 78 79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 80 [ P0 ++ ] = R0; 81 82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 83 [ P0 ++ ] = R0; 84 85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 86 [ P0 ++ ] = R0; 87 88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 89 [ P0 ++ ] = R0; 90 91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 92 [ P0 ++ ] = R0; 93 94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 95 [ P0 ++ ] = R0; 96 97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 98 [ P0 ++ ] = R0; 99 100LD32(p0, EVT_OVERRIDE); 101 R0 = 0; 102 [ P0 ++ ] = R0; 103 R0 = -1; // Change this to mask interrupts (*) 104 [ P0 ] = R0; // IMASK 105CSYNC; 106 107DUMMY: 108 109 R0 = 0 (Z); 110 111LT0 = r0; // set loop counters to something deterministic 112LB0 = r0; 113LC0 = r0; 114LT1 = r0; 115LB1 = r0; 116LC1 = r0; 117 118ASTAT = r0; // reset other internal regs 119 120// The following code sets up the test for running in USER mode 121 122LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 123 // ReturnFromInterrupt (RTI) 124RETI = r0; // We need to load the return address 125 126// Comment the following line for a USER Mode test 127 128JUMP STARTSUP; // jump to code start for SUPERVISOR mode 129 130RTI; 131 132STARTSUP: 133LD32_LABEL(p1, BEGIN); 134 135LD32(p0, EVT15); 136 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 137 138RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in 139 // SUPERVISOR MODE & go to different RAISE in supervisor mode 140 // until the end of the test. 141 142NOP; // Workaround for Bug 217 143RTI; 144 145// 146// The Main Program 147// 148STARTUSER: 149LD32_LABEL(sp, USTACK); // setup the stack pointer 150FP = SP; // set frame pointer 151JUMP BEGIN; 152 153//********************************************************************* 154 155BEGIN: 156 157 // COMMENT the following line for USER MODE tests 158 [ -- SP ] = RETI; // enable interrupts in supervisor mode 159 160 // **** YOUR CODE GOES HERE **** 161R0 = 0; 162ASTAT = R0; 163 // PUT YOUR TEST HERE! 164// PUSH 165LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 166//LD32(p2, DATA_ADDR_1); 167loadsym p2, DATA; 168LD32(p3, 0xab5fd490); 169LD32(p4, 0xa581bd94); 170 171LD32(r2, 0x14789232); 172 [ P1 ] = R2; 173 174 R0 = 0x01; 175 R1 = 0x02; 176 R2 = 0x03; 177 R3 = 0x04; 178 R4 = 0x05; 179 R5 = 0x06; 180 R6 = 0x07; 181 R7 = 0x08; 182 183 [ -- SP ] = ( R7:0 ); 184// RAISE 2; // RTN 185 R0 = [ P2 ++ ]; 186 R1 = [ P1 ]; 187// brf LABEL1 (bp); 188 189 P3 = R7; 190 R4 = P3; 191 [ -- SP ] = ( R7:0 ); 192 R1 = 0x12; 193 R2 = 0x13; 194 R3 = 0x14; 195 R4 = 0x15; 196 R5 = 0x16; 197 R6 = 0x17; 198 R7 = 0x18; 199 200LABEL1: 201// RAISE 5; // RTI 202 R2 = [ P2 ++ ]; 203 R3 = [ P1 ]; 204// brt LABEL2 (bp); // not taken 205 206 P4 = R6; 207 R4 = P4; 208 [ -- SP ] = ( R7:0 ); 209 210 R2 = 0x23; 211 R3 = 0x24; 212 R4 = 0x25; 213 R5 = 0x26; 214 R6 = 0x27; 215 R7 = 0x28; 216 217// wrt-rd EVT5 = 0xFFE02034 218LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 219// RAISE 6; // RTI 220 R4 = [ P2 ++ ]; 221 R5 = [ P1 ]; 222// brf LABEL2 (bp) ; 223 P3 = R3; 224 R6 = P3; 225 [ -- SP ] = ( R7:0 ); 226// POP 227// r0 = 0x00; 228// r1 = 0x00; 229// r2 = 0x00; 230// r3 = 0x00; 231// r4 = 0x00; 232// r5 = 0x00; 233// r6 = 0x00; 234// r7 = 0x00; 235 236LABEL2: 237CSYNC; 238CHECKREG(r0, 0x00010203); 239CHECKREG(r1, 0x00000012); 240CHECKREG(r2, 0x00000023); 241CHECKREG(r3, 0x00000024); 242CHECKREG(r4, 0x00000016); 243CHECKREG(r5, 0x14789232); 244// RAISE 7; // RTI 245 R0 = [ P2 ++ ]; 246 R1 = [ P1 ]; 247 P4 = R4; 248 R2 = P4; 249 ( R7:0 ) = [ SP ++ ]; 250 251 252 253CHECKREG(r0, 0x00010203); 254CHECKREG(r1, 0x00000012); 255CHECKREG(r2, 0x00000023); 256CHECKREG(r3, 0x00000024); 257CHECKREG(r4, 0x00000016); 258CHECKREG(r5, 0x14789232); 259CHECKREG(r6, 0x00000024); 260CHECKREG(r7, 0x00000028); 261// wrt-rd EVT13 = 0xFFE02034 262LD32(p1, 0xFFE02034); 263// RAISE 8; // RTI 264 R0 = [ P2 ++ ]; 265 R1 = [ P1 ]; 266// brf LABEL3; 267 P1 = R5; 268 R6 = P1; 269 ( R7:0 ) = [ SP ++ ]; 270CHECKREG(r0, 0x00010203); // CHECKREG can not be skipped 271CHECKREG(r1, 0x00000012); // so they cannot appear here 272CHECKREG(r2, 0x04050607); 273CHECKREG(r3, 0x14789232); 274CHECKREG(r4, 0x00000017); 275CHECKREG(r5, 0x00000016); 276CHECKREG(r6, 0x00000017); 277CHECKREG(r7, 0x00000018); 278 R0 = 12; 279 R1 = 13; 280 R2 = 14; 281 R3 = 15; 282 R4 = 16; 283 R5 = 17; 284 R6 = 18; 285 R7 = 19; 286 287 288LABEL3: 289CSYNC; 290CHECKREG(r0, 0x0000000C); 291CHECKREG(r1, 0x0000000D); 292// RAISE 9; // RTI 293 P3 = R6; 294 R7 = P3; 295 ( R7:0 ) = [ SP ++ ]; 296 297CHECKREG(r0, 0x00010203); 298CHECKREG(r1, 0x14789232); 299CHECKREG(r2, 0x00000003); 300CHECKREG(r3, 0x00000004); 301CHECKREG(r4, 0x00000008); 302CHECKREG(r5, 0x00000006); 303CHECKREG(r6, 0x00000007); 304CHECKREG(r7, 0x00000008); 305R0 = I0; 306R1 = I1; 307R2 = I2; 308R3 = I3; 309CHECKREG(r0, 0x00000000); 310CHECKREG(r1, 0x00000000); 311CHECKREG(r2, 0x00000000); 312CHECKREG(r3, 0x00000000); 313 314 315END: 316dbg_pass; // End the test 317 318//********************************************************************* 319 320// 321// Handlers for Events 322// 323 324EHANDLE: // Emulation Handler 0 325RTE; 326 327RHANDLE: // Reset Handler 1 328RTI; 329 330NHANDLE: // NMI Handler 2 331 I0 += 2; 332RTN; 333 334XHANDLE: // Exception Handler 3 335 R1 = 3; 336RTX; 337 338HWHANDLE: // HW Error Handler 5 339 I1 += 2; 340RTI; 341 342THANDLE: // Timer Handler 6 343 I2 += 2; 344RTI; 345 346I7HANDLE: // IVG 7 Handler 347 I3 += 2; 348RTI; 349 350I8HANDLE: // IVG 8 Handler 351 I0 += 2; 352RTI; 353 354I9HANDLE: // IVG 9 Handler 355 I0 += 2; 356RTI; 357 358I10HANDLE: // IVG 10 Handler 359 R7 = 10; 360RTI; 361 362I11HANDLE: // IVG 11 Handler 363 I0 = R0; 364 I1 = R1; 365 I2 = R2; 366 I3 = R3; 367 M0 = R4; 368 R0 = 11; 369RTI; 370 371I12HANDLE: // IVG 12 Handler 372 R1 = 12; 373RTI; 374 375I13HANDLE: // IVG 13 Handler 376 R2 = 13; 377RTI; 378 379I14HANDLE: // IVG 14 Handler 380 R3 = 14; 381RTI; 382 383I15HANDLE: // IVG 15 Handler 384 R4 = 15; 385RTI; 386 387NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 388 389// 390// Data Segment 391// 392 393.section MEM_DATA_ADDR_1,"aw" 394DATA: 395// .space (0x10); 396.dd 0x00010203 397.dd 0x04050607 398.dd 0x08090A0B 399.dd 0x0C0D0E0F 400.dd 0x10111213 401.dd 0x14151617 402.dd 0x18191A1B 403.dd 0x1C1D1E1F 404.dd 0x11223344 405.dd 0x55667788 406.dd 0x99717273 407.dd 0x74757677 408.dd 0x82838485 409.dd 0x86878889 410.dd 0x80818283 411.dd 0x84858687 412.dd 0x01020304 413.dd 0x05060708 414.dd 0x09101112 415.dd 0x14151617 416.dd 0x18192021 417 418 419// Stack Segments (Both Kernel and User) 420 421 .space (STACKSIZE); 422KSTACK: 423 424 .space (STACKSIZE); 425USTACK: 426 427.section MEM_DATA_ADDR_2,"aw" 428.dd 0x20212223 429.dd 0x24252627 430.dd 0x28292A2B 431.dd 0x2C2D2E2F 432.dd 0x30313233 433.dd 0x34353637 434.dd 0x38393A3B 435.dd 0x3C3D3E3F 436.dd 0x91929394 437.dd 0x95969798 438.dd 0x99A1A2A3 439.dd 0xA5A6A7A8 440.dd 0xA9B0B1B2 441.dd 0xB3B4B5B6 442.dd 0xB7B8B9C0 443