1//Original:/proj/frio/dv/testcases/seq/se_regmv_usp_sysreg/se_regmv_usp_sysreg.dsp 2// Description: RegMV USP to SYSREG 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10// 11// Constants and Defines 12// 13 14include(selfcheck.inc) 15include(std.inc) 16include(symtable.inc) 17 18//********************************************************************* 19 20BEGIN: 21 22 // KLUDGE: from perl script must place cycles 2 write before cycles 23 // write, and cycles 2 read AFTER cycles read 24 25 // PUT YOUR TEST HERE! 26 R0 = 0; 27SP = R0; 28SYSCFG = R0; 29 30CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); 31 32 R0 = 0x59c4 (Z); 33 R0.H = 0x95a6; 34USP = R0; 35ASTAT = USP; 36 R1 = ASTAT; 37 38 R0 = 0xd4a4 (Z); 39 R0.H = 0xd16c; 40USP = R0; 41RETS = USP; 42 R1 = RETS; 43CHECKREG(r1, 3513570468); 44 45 R0 = 0x2bca (Z); 46 R0.H = 0x6ad8; 47USP = R0; 48LC0 = USP; 49 R1 = LC0; 50CHECKREG(r1, 1792551882); 51 52 R0 = 0x6d4a (Z); 53 R0.H = 0xada2; 54USP = R0; 55LT0 = USP; 56 R1 = LT0; 57CHECKREG(r1, 2913103178); 58 59 R0 = 0x6b18 (Z); 60 R0.H = 0x931c; 61USP = R0; 62LB0 = USP; 63 R1 = LB0; 64CHECKREG(r1, 2468113176); 65 66 R0 = 0x62da (Z); 67 R0.H = 0x16ee; 68USP = R0; 69LC1 = USP; 70 R1 = LC1; 71CHECKREG(r1, 384721626); 72 73 R0 = 0x7c60 (Z); 74 R0.H = 0xf7c8; 75USP = R0; 76LT1 = USP; 77 R1 = LT1; 78CHECKREG(r1, 4157111392); 79 80 R0 = 0x182 (Z); 81 R0.H = 0x942; 82USP = R0; 83LB1 = USP; 84 R1 = LB1; 85CHECKREG(r1, 155320706); 86 87 R0 = 0xd5a2 (Z); 88 R0.H = 0x8782; 89USP = R0; 90CYCLES2 = USP; 91 // KLUDGE - moved read after that for cycles 92 93 R0 = 0x297c (Z); 94 R0.H = 0x9d06; 95USP = R0; 96CYCLES = USP; 97 R1 = CYCLES; 98CHECKREG(r1, 2634426748); 99 R1 = CYCLES2; // KLUDGE moved read after that for cycles 100CHECKREG(r1, 2273498530); 101 102 R0 = 0x8c66 (Z); 103 R0.H = 0x3d64; 104USP = R0; 105SEQSTAT = USP; 106 R1 = SEQSTAT; 107 108 R0 = 0x3b8c (Z); 109 R0.H = 0xdcd4; 110USP = R0; 111SYSCFG = USP; 112 R1 = SYSCFG; 113 114 R0 = 0xb1ae (Z); 115 R0.H = 0x6f6; 116USP = R0; 117RETI = USP; 118 R1 = RETI; 119CHECKREG(r1, 116830638); 120 121 R0 = 0x32b0 (Z); 122 R0.H = 0x9b7e; 123USP = R0; 124RETX = USP; 125 R1 = RETX; 126CHECKREG(r1, 2608738992); 127 128 R0 = 0xea72 (Z); 129 R0.H = 0x11ea; 130USP = R0; 131RETN = USP; 132 R1 = RETN; 133CHECKREG(r1, 300608114); 134 135 R0 = 0x2c58 (Z); 136 R0.H = 0xb13a; 137USP = R0; 138RETE = USP; 139 R1 = RETE; 140CHECKREG(r1, 2973379672); 141 142// Sanity check 143USP = R0; 144USP = R1; 145USP = R2; 146USP = R3; 147USP = R4; 148USP = R5; 149USP = R6; 150USP = R7; 151USP = P0; 152USP = P1; 153USP = P2; 154USP = P3; 155USP = P4; 156USP = P5; 157USP = SP; 158USP = FP; 159USP = A0.X; 160USP = A0.W; 161USP = A1.X; 162USP = A1.W; 163A0.X = USP; 164A0.W = USP; 165A1.X = USP; 166A1.W = USP; 167 168END: 169dbg_pass; // End the test 170 171//********************************************************************* 172