1 /* $NetBSD: smu_v11_0.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __SMU_V11_0_H__ 26 #define __SMU_V11_0_H__ 27 28 #include "amdgpu_smu.h" 29 30 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF 31 #define SMU11_DRIVER_IF_VERSION_VG20 0x13 32 #define SMU11_DRIVER_IF_VERSION_ARCT 0x12 33 #define SMU11_DRIVER_IF_VERSION_NV10 0x33 34 #define SMU11_DRIVER_IF_VERSION_NV14 0x34 35 36 /* MP Apertures */ 37 #define MP0_Public 0x03800000 38 #define MP0_SRAM 0x03900000 39 #define MP1_Public 0x03b00000 40 #define MP1_SRAM 0x03c00004 41 #define MP1_SMC_SIZE 0x40000 42 43 /* address block */ 44 #define smnMP1_FIRMWARE_FLAGS 0x3010024 45 #define smnMP0_FW_INTF 0x30101c0 46 #define smnMP1_PUB_CTRL 0x3010b14 47 48 #define TEMP_RANGE_MIN (0) 49 #define TEMP_RANGE_MAX (80 * 1000) 50 51 #define SMU11_TOOL_SIZE 0x19000 52 53 #define MAX_PCIE_CONF 2 54 55 #define CLK_MAP(clk, index) \ 56 [SMU_##clk] = {1, (index)} 57 58 #define FEA_MAP(fea) \ 59 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 60 61 #define TAB_MAP(tab) \ 62 [SMU_TABLE_##tab] = {1, TABLE_##tab} 63 64 #define PWR_MAP(tab) \ 65 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 66 67 #define WORKLOAD_MAP(profile, workload) \ 68 [profile] = {1, (workload)} 69 70 static const struct smu_temperature_range smu11_thermal_policy[] = 71 { 72 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 73 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 74 }; 75 76 struct smu_11_0_cmn2aisc_mapping { 77 int valid_mapping; 78 int map_to; 79 }; 80 81 struct smu_11_0_max_sustainable_clocks { 82 uint32_t display_clock; 83 uint32_t phy_clock; 84 uint32_t pixel_clock; 85 uint32_t uclock; 86 uint32_t dcef_clock; 87 uint32_t soc_clock; 88 }; 89 90 struct smu_11_0_dpm_table { 91 uint32_t min; /* MHz */ 92 uint32_t max; /* MHz */ 93 }; 94 95 struct smu_11_0_pcie_table { 96 uint8_t pcie_gen[MAX_PCIE_CONF]; 97 uint8_t pcie_lane[MAX_PCIE_CONF]; 98 }; 99 100 struct smu_11_0_dpm_tables { 101 struct smu_11_0_dpm_table soc_table; 102 struct smu_11_0_dpm_table gfx_table; 103 struct smu_11_0_dpm_table uclk_table; 104 struct smu_11_0_dpm_table eclk_table; 105 struct smu_11_0_dpm_table vclk_table; 106 struct smu_11_0_dpm_table dclk_table; 107 struct smu_11_0_dpm_table dcef_table; 108 struct smu_11_0_dpm_table pixel_table; 109 struct smu_11_0_dpm_table display_table; 110 struct smu_11_0_dpm_table phy_table; 111 struct smu_11_0_dpm_table fclk_table; 112 struct smu_11_0_pcie_table pcie_table; 113 }; 114 115 struct smu_11_0_dpm_context { 116 struct smu_11_0_dpm_tables dpm_tables; 117 uint32_t workload_policy_mask; 118 uint32_t dcef_min_ds_clk; 119 }; 120 121 enum smu_11_0_power_state { 122 SMU_11_0_POWER_STATE__D0 = 0, 123 SMU_11_0_POWER_STATE__D1, 124 SMU_11_0_POWER_STATE__D3, /* Sleep*/ 125 SMU_11_0_POWER_STATE__D4, /* Hibernate*/ 126 SMU_11_0_POWER_STATE__D5, /* Power off*/ 127 }; 128 129 struct smu_11_0_power_context { 130 uint32_t power_source; 131 uint8_t in_power_limit_boost_mode; 132 enum smu_11_0_power_state power_state; 133 }; 134 135 enum smu_v11_0_baco_seq { 136 BACO_SEQ_BACO = 0, 137 BACO_SEQ_MSR, 138 BACO_SEQ_BAMACO, 139 BACO_SEQ_ULPS, 140 BACO_SEQ_COUNT, 141 }; 142 143 int smu_v11_0_init_microcode(struct smu_context *smu); 144 145 int smu_v11_0_load_microcode(struct smu_context *smu); 146 147 int smu_v11_0_init_smc_tables(struct smu_context *smu); 148 149 int smu_v11_0_fini_smc_tables(struct smu_context *smu); 150 151 int smu_v11_0_init_power(struct smu_context *smu); 152 153 int smu_v11_0_fini_power(struct smu_context *smu); 154 155 int smu_v11_0_check_fw_status(struct smu_context *smu); 156 157 int smu_v11_0_setup_pptable(struct smu_context *smu); 158 159 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu); 160 161 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu); 162 163 int smu_v11_0_check_pptable(struct smu_context *smu); 164 165 int smu_v11_0_parse_pptable(struct smu_context *smu); 166 167 int smu_v11_0_populate_smc_pptable(struct smu_context *smu); 168 169 int smu_v11_0_check_fw_version(struct smu_context *smu); 170 171 int smu_v11_0_write_pptable(struct smu_context *smu); 172 173 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu); 174 175 int smu_v11_0_set_driver_table_location(struct smu_context *smu); 176 177 int smu_v11_0_set_tool_table_location(struct smu_context *smu); 178 179 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu); 180 181 int smu_v11_0_system_features_control(struct smu_context *smu, 182 bool en); 183 184 int 185 smu_v11_0_send_msg_with_param(struct smu_context *smu, 186 enum smu_message_type msg, 187 uint32_t param); 188 189 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg); 190 191 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count); 192 193 int smu_v11_0_set_allowed_mask(struct smu_context *smu); 194 195 int smu_v11_0_get_enabled_mask(struct smu_context *smu, 196 uint32_t *feature_mask, uint32_t num); 197 198 int smu_v11_0_notify_display_change(struct smu_context *smu); 199 200 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n); 201 202 int smu_v11_0_get_current_clk_freq(struct smu_context *smu, 203 enum smu_clk_type clk_id, 204 uint32_t *value); 205 206 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu); 207 208 int smu_v11_0_start_thermal_control(struct smu_context *smu); 209 210 int smu_v11_0_stop_thermal_control(struct smu_context *smu); 211 212 int smu_v11_0_read_sensor(struct smu_context *smu, 213 enum amd_pp_sensors sensor, 214 void *data, uint32_t *size); 215 216 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 217 218 int 219 smu_v11_0_display_clock_voltage_request(struct smu_context *smu, 220 struct pp_display_clock_request 221 *clock_req); 222 223 uint32_t 224 smu_v11_0_get_fan_control_mode(struct smu_context *smu); 225 226 int 227 smu_v11_0_set_fan_control_mode(struct smu_context *smu, 228 uint32_t mode); 229 230 int 231 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed); 232 233 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, 234 uint32_t speed); 235 236 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, 237 uint32_t pstate); 238 239 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable); 240 241 int smu_v11_0_register_irq_handler(struct smu_context *smu); 242 243 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu); 244 245 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 246 struct pp_smu_nv_clock_table *max_clocks); 247 248 bool smu_v11_0_baco_is_support(struct smu_context *smu); 249 250 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu); 251 252 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 253 254 int smu_v11_0_baco_enter(struct smu_context *smu); 255 int smu_v11_0_baco_exit(struct smu_context *smu); 256 257 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 258 uint32_t *min, uint32_t *max); 259 260 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 261 uint32_t min, uint32_t max); 262 263 int smu_v11_0_override_pcie_parameters(struct smu_context *smu); 264 265 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size); 266 267 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu); 268 269 int smu_v11_0_set_performance_level(struct smu_context *smu, 270 enum amd_dpm_forced_level level); 271 272 #endif 273