1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty.
5// SPDX-License-Identifier: CC0-1.0
6
7// bug998
8
9interface intf
10  #(parameter PARAM = 0)
11   ();
12   logic val;
13   function integer func (); return 5; endfunction
14endinterface
15
16module t1(intf mod_intf);
17   initial begin
18      $display("%m %d", mod_intf.val);
19   end
20endmodule
21
22module t();
23   generate
24      begin : TestIf
25         intf #(.PARAM(1)) my_intf ();
26         assign my_intf.val = '0;
27         t1 t (.mod_intf(my_intf));
28//         initial $display("%0d", my_intf.func());
29      end
30   endgenerate
31
32   generate
33      begin
34         intf #(.PARAM(1)) my_intf ();
35         assign my_intf.val = '1;
36         t1 t (.mod_intf(my_intf));
37//         initial $display("%0d", my_intf.func());
38      end
39   endgenerate
40
41   localparam LP = 1;
42   logic val;
43
44   generate begin
45      if (LP) begin
46         intf #(.PARAM(2)) my_intf ();
47         assign my_intf.val = '1;
48         assign val = my_intf.val;
49      end else begin
50         intf #(.PARAM(3)) my_intf ();
51         assign my_intf.val = '1;
52         assign val = my_intf.val;
53      end
54   end endgenerate
55
56   initial begin
57      $display("%0d", val);
58      $write("*-* All Finished *-*\n");
59      $finish;
60   end
61endmodule
62