1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2010 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk, rst_both_l, rst_sync_l, rst_async_l, d 10 ); 11 /*AUTOINPUT*/ 12 13 input clk; 14 input rst_both_l; 15 input rst_sync_l; 16 input rst_async_l; 17 18 input d; 19 reg q1; 20 reg q2; 21 22 always @(posedge clk) begin 23 if (~rst_sync_l) begin 24 /*AUTORESET*/ 25 // Beginning of autoreset for uninitialized flops 26 q1 <= 1'h0; 27 // End of automatics 28 end else begin 29 q1 <= d; 30 end 31 end 32 33 always @(posedge clk) begin 34 q2 <= (rst_both_l) ? d : 1'b0; 35 if (0 && q1 && q2) ; 36 end 37 38 reg q3; 39 always @(posedge clk or negedge rst_async_l) begin 40 if (~rst_async_l) begin 41 /*AUTORESET*/ 42 // Beginning of autoreset for uninitialized flops 43 q3 <= 1'h0; 44 // End of automatics 45 end else begin 46 q3 <= d; 47 end 48 end 49 50 reg q4; 51 always @(posedge clk or negedge rst_both_l) begin 52 q4 <= (~rst_both_l) ? 1'b0 : d; 53 end 54 // Make there be more async uses than sync uses 55 reg q5; 56 always @(posedge clk or negedge rst_both_l) begin 57 q5 <= (~rst_both_l) ? 1'b0 : d; 58 if (0 && q3 && q4 && q5) ; 59 end 60 61endmodule 62