1// DESCRIPTION: Verilator: Verilog Test module
2// This file ONLY is placed under the Creative Commons Public Domain, for
3// any use, without warranty, 2020 by Wilson Snyder.
4// SPDX-License-Identifier: CC0-1.0
5
6module foo
7#( parameter real bar = 2.0)
8();
9
10endmodule
11
12module t();
13
14   genvar m, r;
15   generate
16      for (m = 10; m <= 20; m+=10) begin : gen_m
17         for (r = 0; r <= 1; r++) begin : gen_r
18            localparam real lparam = m + (r + 0.5);
19            initial begin
20                if (lparam != foo_inst.bar) begin
21                   $display("%m: lparam != foo_inst.bar (%f, %f)",
22                            lparam, foo_inst.bar);
23                   $stop();
24                end
25            end
26
27            foo #(.bar (lparam)) foo_inst ();
28         end
29      end
30   endgenerate
31
32   initial begin
33      $write("*-* All Finished *-*\n");
34      $finish;
35   end
36
37endmodule
38