1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2018 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"}; 15 16 initial begin 17 $display("%s", SVEC[3'd1]); 18 $write("*-* All Finished *-*\n"); 19 $finish; 20 end 21 22 localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 23 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; 24 25 function string regx (logic [5-1:0] r, bit abi=1'b0); 26 regx = abi ? REGX[r] : $sformatf("x%0d", r); 27 endfunction: regx 28 29 function string dis32 (logic [32-1:0] op); 30 casez (op) 31 32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop"); 32 32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-"); 33 32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)", 34 regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0])); 35 default: dis32 = "illegal"; 36 endcase 37 endfunction: dis32 38 39 always @(posedge clk) begin 40 for (int unsigned i=0; i<32; i++) 41 $display("REGX: %s", regx(i[4:0])); 42 $display("OP: %s", dis32(32'h00000000)); 43 $finish(); 44 end 45 46endmodule 47