1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2010 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7// Try inline config 8`ifdef verilator 9 `verilator_config 10 lint_off -rule CASEX -file "t/t_vlt_warn.v" 11 `verilog 12`endif 13 14 15 16 17 18module t; 19 reg width_warn_var_line18 = 2'b11; // Width warning - must be line 18 20 reg width_warn2_var_line19 = 2'b11; // Width warning - must be line 19 21 reg width_warn3_var_line20 = 2'b11; // Width warning - must be line 20 22 23 initial begin 24 casex (1'b1) 25 1'b0: $stop; 26 endcase 27 28 $write("*-* All Finished *-*\n"); 29 $finish; 30 end 31endmodule 32