1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__ 27 #define __DAL_TIMING_GENERATOR_TYPES_H__ 28 29 #include "hw_shared.h" 30 31 struct dc_bios; 32 33 /* Contains CRTC vertical/horizontal pixel counters */ 34 struct crtc_position { 35 int32_t vertical_count; 36 int32_t horizontal_count; 37 int32_t nominal_vcount; 38 }; 39 40 struct dcp_gsl_params { 41 int gsl_group; 42 int gsl_master; 43 }; 44 45 struct gsl_params { 46 int gsl0_en; 47 int gsl1_en; 48 int gsl2_en; 49 int gsl_master_en; 50 int gsl_master_mode; 51 int master_update_lock_gsl_en; 52 int gsl_window_start_x; 53 int gsl_window_end_x; 54 int gsl_window_start_y; 55 int gsl_window_end_y; 56 }; 57 58 /* define the structure of Dynamic Refresh Mode */ 59 struct drr_params { 60 uint32_t vertical_total_min; 61 uint32_t vertical_total_max; 62 uint32_t vertical_total_mid; 63 uint32_t vertical_total_mid_frame_num; 64 bool immediate_flip; 65 }; 66 67 struct long_vtotal_params { 68 uint32_t vertical_total_min; 69 uint32_t vertical_total_max; 70 uint32_t vertical_blank_start; 71 }; 72 73 #define LEFT_EYE_3D_PRIMARY_SURFACE 1 74 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0 75 76 enum crtc_state { 77 CRTC_STATE_VBLANK = 0, 78 CRTC_STATE_VACTIVE 79 }; 80 81 struct vupdate_keepout_params { 82 int start_offset; 83 int end_offset; 84 int enable; 85 }; 86 87 struct crtc_stereo_flags { 88 uint8_t PROGRAM_STEREO : 1; 89 uint8_t PROGRAM_POLARITY : 1; 90 uint8_t RIGHT_EYE_POLARITY : 1; 91 uint8_t FRAME_PACKED : 1; 92 uint8_t DISABLE_STEREO_DP_SYNC : 1; 93 }; 94 95 enum crc_selection { 96 /* Order must match values expected by hardware */ 97 UNION_WINDOW_A_B = 0, 98 UNION_WINDOW_A_NOT_B, 99 UNION_WINDOW_NOT_A_B, 100 UNION_WINDOW_NOT_A_NOT_B, 101 INTERSECT_WINDOW_A_B, 102 INTERSECT_WINDOW_A_NOT_B, 103 INTERSECT_WINDOW_NOT_A_B, 104 INTERSECT_WINDOW_NOT_A_NOT_B, 105 }; 106 107 enum otg_out_mux_dest { 108 OUT_MUX_DIO = 0, 109 OUT_MUX_HPO_DP = 2, 110 }; 111 112 enum h_timing_div_mode { 113 H_TIMING_NO_DIV, 114 H_TIMING_DIV_BY2, 115 H_TIMING_RESERVED, 116 H_TIMING_DIV_BY4, 117 }; 118 119 enum timing_synchronization_type { 120 NOT_SYNCHRONIZABLE, 121 TIMING_SYNCHRONIZABLE, 122 VBLANK_SYNCHRONIZABLE 123 }; 124 125 struct crc_params { 126 /* Regions used to calculate CRC*/ 127 uint16_t windowa_x_start; 128 uint16_t windowa_x_end; 129 uint16_t windowa_y_start; 130 uint16_t windowa_y_end; 131 132 uint16_t windowb_x_start; 133 uint16_t windowb_x_end; 134 uint16_t windowb_y_start; 135 uint16_t windowb_y_end; 136 137 enum crc_selection selection; 138 139 uint8_t dsc_mode; 140 uint8_t odm_mode; 141 142 bool continuous_mode; 143 bool enable; 144 }; 145 146 /** 147 * struct timing_generator - Entry point to Output Timing Generator feature. 148 */ 149 struct timing_generator { 150 /** 151 * @funcs: Timing generator control functions 152 */ 153 const struct timing_generator_funcs *funcs; 154 struct dc_bios *bp; 155 struct dc_context *ctx; 156 int inst; 157 }; 158 159 struct dc_crtc_timing; 160 161 struct drr_params; 162 163 /** 164 * struct timing_generator_funcs - Control timing generator on a given device. 165 */ 166 struct timing_generator_funcs { 167 bool (*validate_timing)(struct timing_generator *tg, 168 const struct dc_crtc_timing *timing); 169 void (*program_timing)(struct timing_generator *tg, 170 const struct dc_crtc_timing *timing, 171 int vready_offset, 172 int vstartup_start, 173 int vupdate_offset, 174 int vupdate_width, 175 const enum signal_type signal, 176 bool use_vbios 177 ); 178 void (*setup_vertical_interrupt0)( 179 struct timing_generator *optc, 180 uint32_t start_line, 181 uint32_t end_line); 182 void (*setup_vertical_interrupt1)( 183 struct timing_generator *optc, 184 uint32_t start_line); 185 void (*setup_vertical_interrupt2)( 186 struct timing_generator *optc, 187 uint32_t start_line); 188 189 bool (*enable_crtc)(struct timing_generator *tg); 190 bool (*disable_crtc)(struct timing_generator *tg); 191 void (*phantom_crtc_post_enable)(struct timing_generator *tg); 192 void (*disable_phantom_crtc)(struct timing_generator *tg); 193 bool (*immediate_disable_crtc)(struct timing_generator *tg); 194 bool (*is_counter_moving)(struct timing_generator *tg); 195 void (*get_position)(struct timing_generator *tg, 196 struct crtc_position *position); 197 198 uint32_t (*get_frame_count)(struct timing_generator *tg); 199 void (*get_scanoutpos)( 200 struct timing_generator *tg, 201 uint32_t *v_blank_start, 202 uint32_t *v_blank_end, 203 uint32_t *h_position, 204 uint32_t *v_position); 205 bool (*get_otg_active_size)(struct timing_generator *optc, 206 uint32_t *otg_active_width, 207 uint32_t *otg_active_height); 208 bool (*is_matching_timing)(struct timing_generator *tg, 209 const struct dc_crtc_timing *otg_timing); 210 void (*set_early_control)(struct timing_generator *tg, 211 uint32_t early_cntl); 212 void (*wait_for_state)(struct timing_generator *tg, 213 enum crtc_state state); 214 void (*set_blank)(struct timing_generator *tg, 215 bool enable_blanking); 216 bool (*is_blanked)(struct timing_generator *tg); 217 void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); 218 void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color); 219 void (*set_colors)(struct timing_generator *tg, 220 const struct tg_color *blank_color, 221 const struct tg_color *overscan_color); 222 223 void (*disable_vga)(struct timing_generator *tg); 224 bool (*did_triggered_reset_occur)(struct timing_generator *tg); 225 void (*setup_global_swap_lock)(struct timing_generator *tg, 226 const struct dcp_gsl_params *gsl_params); 227 void (*unlock)(struct timing_generator *tg); 228 void (*lock)(struct timing_generator *tg); 229 void (*lock_doublebuffer_disable)(struct timing_generator *tg); 230 void (*lock_doublebuffer_enable)(struct timing_generator *tg); 231 void(*triplebuffer_unlock)(struct timing_generator *tg); 232 void(*triplebuffer_lock)(struct timing_generator *tg); 233 void (*enable_reset_trigger)(struct timing_generator *tg, 234 int source_tg_inst); 235 void (*enable_crtc_reset)(struct timing_generator *tg, 236 int source_tg_inst, 237 struct crtc_trigger_info *crtc_tp); 238 void (*disable_reset_trigger)(struct timing_generator *tg); 239 void (*tear_down_global_swap_lock)(struct timing_generator *tg); 240 void (*enable_advanced_request)(struct timing_generator *tg, 241 bool enable, const struct dc_crtc_timing *timing); 242 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); 243 void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max); 244 void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate); 245 void (*set_static_screen_control)(struct timing_generator *tg, 246 uint32_t event_triggers, 247 uint32_t num_frames); 248 void (*set_test_pattern)( 249 struct timing_generator *tg, 250 enum controller_dp_test_pattern test_pattern, 251 enum dc_color_depth color_depth); 252 253 bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); 254 255 void (*program_global_sync)(struct timing_generator *tg, 256 int vready_offset, 257 int vstartup_start, 258 int vupdate_offset, 259 int vupdate_width); 260 void (*enable_optc_clock)(struct timing_generator *tg, bool enable); 261 void (*program_stereo)(struct timing_generator *tg, 262 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 263 bool (*is_stereo_left_eye)(struct timing_generator *tg); 264 265 void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); 266 267 void (*tg_init)(struct timing_generator *tg); 268 bool (*is_tg_enabled)(struct timing_generator *tg); 269 bool (*is_optc_underflow_occurred)(struct timing_generator *tg); 270 void (*clear_optc_underflow)(struct timing_generator *tg); 271 272 void (*set_dwb_source)(struct timing_generator *optc, 273 uint32_t dwb_pipe_inst); 274 275 void (*get_optc_source)(struct timing_generator *optc, 276 uint32_t *num_of_input_segments, 277 uint32_t *seg0_src_sel, 278 uint32_t *seg1_src_sel); 279 280 /** 281 * Configure CRCs for the given timing generator. Return false if TG is 282 * not on. 283 */ 284 bool (*configure_crc)(struct timing_generator *tg, 285 const struct crc_params *params); 286 287 /** 288 * @get_crc: Get CRCs for the given timing generator. Return false if 289 * CRCs are not enabled (via configure_crc). 290 */ 291 bool (*get_crc)(struct timing_generator *tg, 292 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 293 294 void (*program_manual_trigger)(struct timing_generator *optc); 295 void (*setup_manual_trigger)(struct timing_generator *optc); 296 bool (*get_hw_timing)(struct timing_generator *optc, 297 struct dc_crtc_timing *hw_crtc_timing); 298 299 void (*set_vtg_params)(struct timing_generator *optc, 300 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 301 302 void (*set_dsc_config)(struct timing_generator *optc, 303 enum optc_dsc_mode dsc_mode, 304 uint32_t dsc_bytes_per_pixel, 305 uint32_t dsc_slice_width); 306 void (*get_dsc_status)(struct timing_generator *optc, 307 uint32_t *dsc_mode); 308 void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); 309 310 /** 311 * @set_odm_combine: Set up the ODM block to read from the correct 312 * OPP(s) and turn on/off ODM memory. 313 */ 314 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, 315 struct dc_crtc_timing *timing); 316 void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments); 317 void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode); 318 void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); 319 void (*set_gsl_source_select)(struct timing_generator *optc, 320 int group_idx, 321 uint32_t gsl_ready_signal); 322 void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest); 323 void (*set_drr_trigger_window)(struct timing_generator *optc, 324 uint32_t window_start, uint32_t window_end); 325 void (*set_vtotal_change_limit)(struct timing_generator *optc, 326 uint32_t limit); 327 void (*align_vblanks)(struct timing_generator *master_optc, 328 struct timing_generator *slave_optc, 329 uint32_t master_pixel_clock_100Hz, 330 uint32_t slave_pixel_clock_100Hz, 331 uint8_t master_clock_divider, 332 uint8_t slave_clock_divider); 333 bool (*validate_vmin_vmax)(struct timing_generator *optc, 334 int vmin, int vmax); 335 bool (*validate_vtotal_change_limit)(struct timing_generator *optc, 336 uint32_t vtotal_change_limit); 337 338 void (*init_odm)(struct timing_generator *tg); 339 void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); 340 void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); 341 void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); 342 }; 343 344 #endif 345