xref: /original-bsd/sys/vax/uba/ubareg.h (revision 22da2062)
1 /*-
2  * Copyright (c) 1982, 1986
3  *	The Regents of the University of California.  All rights reserved.
4  * (c) UNIX System Laboratories, Inc.
5  * All or some portions of this file are derived from material licensed
6  * to the University of California by American Telephone and Telegraph
7  * Co. or Unix System Laboratories, Inc. and are reproduced herein with
8  * the permission of UNIX System Laboratories, Inc.
9  *
10  * %sccs.include.redist.c%
11  *
12  *	@(#)ubareg.h	7.9 (Berkeley) 01/21/94
13  */
14 
15 /*
16  * VAX UNIBUS adapter registers
17  */
18 
19 /*
20  * "UNIBUS" adaptor types.
21  * This code is used for both UNIBUSes and Q-buses
22  * with different types of adaptors.
23  * Definition of a type includes support code for that type.
24  */
25 #if VAX780 || VAX8600
26 #define	DW780	1		/* has adaptor regs, sr: 780/785/8600 */
27 #endif
28 
29 #if VAX750
30 #define	DW750	2		/* has adaptor regs, no sr: 750, 730 */
31 #endif
32 
33 #if VAX730
34 #define	DW730	3		/* has adaptor regs, no sr: 750, 730 */
35 #endif
36 
37 #if VAX630 || VAX650
38 #define	QBA	4		/* 22-bit Q-bus, no adaptor regs: uVAX II */
39 #endif
40 
41 #if VAX8200 || VAX8500 || VAX8800
42 #define	DWBUA	5		/* BI UNIBUS adaptor: 8200/8500/8800 */
43 #endif
44 
45 /*
46  * Size of unibus memory address space in pages
47  * (also number of map registers).
48  * QBAPAGES should be 8192, but we don't need nearly that much
49  * address space, and the return from the allocation routine
50  * can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
51  * QBAPAGES must be at least UBAPAGES.  Choose pragmatically.
52  */
53 #define	UBAPAGES	496
54 #define	NUBMREG		496
55 #if defined(GATEWAY) && !defined(QNIVERT)
56 #define	QBAPAGES	1024
57 #else
58 #define	QBAPAGES	UBAPAGES
59 #endif
60 #define	UBAIOADDR	0760000		/* start of I/O page */
61 #define	UBAIOPAGES	16
62 
63 #ifndef LOCORE
64 /*
65  * DWBUA hardware registers.
66  */
67 struct dwbua_regs {
68 	int	pad1[456];		/* actually bii regs + pad */
69 	int	bua_csr;		/* control and status register */
70 	int	bua_offset;		/* vector offset register */
71 	int	bua_fubar;		/* failed UNIBUS address register */
72 	int	bua_bifar;		/* BI failed address register */
73 	int	bua_udiag[5];		/* micro diagnostics (R/O) */
74 	int	pad2[3];
75 /* dpr[0] is for DDP; dpr's 1 through 5 are for BPD's 1 through 5 */
76 	int	bua_dpr[6];		/* data path registers */
77 	int	pad3[10];
78 	int	bua_bdps[20];		/* buffered data path space *//*???*/
79 	int	pad4[8];
80 	struct	pte bua_map[UBAPAGES];	/* unibus map registers */
81 	int	pad5[UBAIOPAGES];	/* no maps for device address space */
82 };
83 
84 #ifdef DWBUA
85 /* bua_csr */
86 #define	BUACSR_ERR	0x80000000	/* composite error */
87 #define	BUACSR_BIF	0x10000000	/* BI failure */
88 #define	BUACSR_SSYNTO	0x08000000	/* slave sync timeout */
89 #define	BUACSR_UIE	0x04000000	/* unibus interlock error */
90 #define	BUACSR_IVMR	0x02000000	/* invalid map register */
91 #define	BUACSR_BADBDP	0x01000000	/* bad BDP select */
92 #define	BUACSR_BUAEIE	0x00100000	/* bua error interrupt enable (?) */
93 #define	BUACSR_UPI	0x00020000	/* unibus power init */
94 #define	BUACSR_UREGDUMP	0x00010000	/* microdiag register dump */
95 #define	BUACSR_IERRNO	0x000000ff	/* mask for internal errror number */
96 
97 /* bua_offset */
98 #define	BUAOFFSET_MASK	0x00003e00	/* hence max offset = 15872 */
99 
100 /* bua_dpr */
101 #define	BUADPR_DPSEL	0x00e00000	/* data path select (?) */
102 #define	BUADPR_PURGE	0x00000001	/* purge bdp */
103 
104 /* bua_map -- in particular, those bits that are not in DW780s & DW750s */
105 #define	BUAMR_IOADR	0x40000000	/* I/O address space */
106 #define	BUAMR_LAE	0x04000000	/* longword access enable */
107 	/* I see no reason to use either one, though ... act 6 Aug 1987 */
108 
109 #define	UBA_PURGEBUA(uba, bdp) \
110 	(((struct dwbua_regs *)(uba))->bua_dpr[bdp] |= BUADPR_PURGE)
111 #else
112 #define	UBA_PURGEBUA(uba, bdp)
113 #endif
114 
115 /*
116  * DW780/DW750 hardware registers
117  */
118 struct uba_regs {
119 	int	uba_cnfgr;		/* configuration register */
120 	int	uba_cr;			/* control register */
121 	int	uba_sr;			/* status register */
122 	int	uba_dcr;		/* diagnostic control register */
123 	int	uba_fmer;		/* failed map entry register */
124 	int	uba_fubar;		/* failed UNIBUS address register */
125 	int	pad1[2];
126 	int	uba_brsvr[4];
127 	int	uba_brrvr[4];		/* receive vector registers */
128 	int	uba_dpr[16];		/* buffered data path register */
129 	int	pad2[480];
130 	struct	pte uba_map[UBAPAGES];	/* unibus map register */
131 	int	pad3[UBAIOPAGES];	/* no maps for device address space */
132 };
133 #endif
134 
135 #ifdef DW780
136 /* uba_cnfgr */
137 #define	UBACNFGR_UBINIT	0x00040000	/* unibus init asserted */
138 #define	UBACNFGR_UBPDN	0x00020000	/* unibus power down */
139 #define	UBACNFGR_UBIC	0x00010000	/* unibus init complete */
140 
141 #define UBACNFGR_BITS \
142 "\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
143 
144 /* uba_cr */
145 #define	UBACR_MRD16	0x40000000	/* map reg disable bit 4 */
146 #define	UBACR_MRD8	0x20000000	/* map reg disable bit 3 */
147 #define	UBACR_MRD4	0x10000000	/* map reg disable bit 2 */
148 #define	UBACR_MRD2	0x08000000	/* map reg disable bit 1 */
149 #define	UBACR_MRD1	0x04000000	/* map reg disable bit 0 */
150 #define	UBACR_IFS	0x00000040	/* interrupt field switch */
151 #define	UBACR_BRIE	0x00000020	/* BR interrupt enable */
152 #define	UBACR_USEFIE	0x00000010	/* UNIBUS to SBI error field IE */
153 #define	UBACR_SUEFIE	0x00000008	/* SBI to UNIBUS error field IE */
154 #define	UBACR_CNFIE	0x00000004	/* configuration IE */
155 #define	UBACR_UPF	0x00000002	/* UNIBUS power fail */
156 #define	UBACR_ADINIT	0x00000001	/* adapter init */
157 
158 /* uba_sr */
159 #define	UBASR_BR7FULL	0x08000000	/* BR7 receive vector reg full */
160 #define	UBASR_BR6FULL	0x04000000	/* BR6 receive vector reg full */
161 #define	UBASR_BR5FULL	0x02000000	/* BR5 receive vector reg full */
162 #define	UBASR_BR4FULL	0x01000000	/* BR4 receive vector reg full */
163 #define	UBASR_RDTO	0x00000400	/* UNIBUS to SBI read data timeout */
164 #define	UBASR_RDS	0x00000200	/* read data substitute */
165 #define	UBASR_CRD	0x00000100	/* corrected read data */
166 #define	UBASR_CXTER	0x00000080	/* command transmit error */
167 #define	UBASR_CXTMO	0x00000040	/* command transmit timeout */
168 #define	UBASR_DPPE	0x00000020	/* data path parity error */
169 #define	UBASR_IVMR	0x00000010	/* invalid map register */
170 #define	UBASR_MRPF	0x00000008	/* map register parity failure */
171 #define	UBASR_LEB	0x00000004	/* lost error */
172 #define	UBASR_UBSTO	0x00000002	/* UNIBUS select timeout */
173 #define	UBASR_UBSSYNTO	0x00000001	/* UNIBUS slave sync timeout */
174 
175 #define	UBASR_BITS \
176 "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
177 
178 /* uba_brrvr[] */
179 #define	UBABRRVR_AIRI	0x80000000	/* adapter interrupt request */
180 #define	UBABRRVR_DIV	0x0000ffff	/* device interrupt vector field */
181 #endif
182 
183 /* uba_dpr */
184 #ifdef DW780
185 #define	UBADPR_BNE	0x80000000	/* buffer not empty - purge */
186 #define	UBADPR_BTE	0x40000000	/* buffer transfer error */
187 #define	UBADPR_DPF	0x20000000	/* DP function (RO) */
188 #define	UBADPR_BS	0x007f0000	/* buffer state field */
189 #define	UBADPR_BUBA	0x0000ffff	/* buffered UNIBUS address */
190 #define	UBA_PURGE780(uba, bdp) \
191     ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
192 #else
193 #define UBA_PURGE780(uba, bdp)
194 #endif
195 #ifdef DW750
196 #define	UBADPR_ERROR	0x80000000	/* error occurred */
197 #define	UBADPR_NXM	0x40000000	/* nxm from memory */
198 #define	UBADPR_UCE	0x20000000	/* uncorrectable error */
199 #define	UBADPR_PURGE	0x00000001	/* purge bdp */
200 /* the DELAY is for a hardware problem */
201 #define	UBA_PURGE750(uba, bdp) { \
202     ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
203     DELAY(8); \
204 }
205 #else
206 #define UBA_PURGE750(uba, bdp)
207 #endif
208 
209 /*
210  * Macros for fast buffered data path purging in time-critical routines.
211  *
212  * Too bad C pre-processor doesn't have the power of LISP in macro
213  * expansion...
214  */
215 
216 /* THIS IS WRONG, should use pointer to uba_hd */
217 #if DWBUA || DW780 || DW750
218 #define	UBAPURGE(uba, bdp) { \
219 	switch (cpu) { \
220 	case VAX_8200: UBA_PURGEBUA(uba, bdp); break; \
221 	case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
222 	case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
223 	} \
224 }
225 #else
226 #define	UBAPURGE(uba, bdp)
227 #endif
228 
229 
230 
231 /* uba_mr[] */
232 #define	UBAMR_MRV	0x80000000	/* map register valid */
233 #define	UBAMR_BO	0x02000000	/* byte offset bit */
234 #define	UBAMR_DPDB	0x01e00000	/* data path designator field */
235 #define	UBAMR_SBIPFN	0x001fffff	/* SBI page address field */
236 
237 #define	UBAMR_DPSHIFT	21		/* shift to data path designator */
238 
239 /*
240  * Number of unibus buffered data paths and possible uba's per cpu type.
241  */
242 #define	NBDP8600	15
243 #define	NBDP780		15
244 #define	NBDPBUA		5
245 #define	NBDP750		3
246 #define	NBDP730		0
247 #define	MAXNBDP		15
248 
249 /*
250  * Symbolic BUS addresses for UBAs.
251  */
252 
253 #if VAX630 || VAX650
254 #define	QBAMAP630	((struct pte *)0x20088000)
255 #define	QMEM630		0x30000000
256 #define	QIOPAGE630	0x20000000
257 /*
258  * Q-bus control registers
259  */
260 #define	QIPCR		0x1f40		/* from start of iopage */
261 /* bits in QIPCR */
262 #define	Q_DBIRQ		0x0001		/* doorbell interrupt request */
263 #define	Q_LMEAE		0x0020		/* local mem external access enable */
264 #define	Q_DBIIE		0x0040		/* doorbell interrupt enable */
265 #define	Q_AUXHLT	0x0100		/* auxiliary processor halt */
266 #define	Q_DMAQPE	0x8000		/* Q22 bus address space parity error */
267 #endif
268 
269 #if VAX730
270 #define	UMEM730		0xfc0000
271 #endif
272 
273 #if VAX750
274 #define	UMEM750(i)	(0xfc0000-(i)*0x40000)
275 #endif
276 
277 #if VAX780
278 #define	UMEM780(i)	(0x20100000+(i)*0x40000)
279 #endif
280 
281 #if VAX8200		/* BEWARE, argument is node, not ubanum */
282 #define	UMEM8200(i)	(0x20400000+(i)*0x40000)
283 #endif
284 
285 #if VAX8600
286 #define	UMEMA8600(i)	(0x20100000+(i)*0x40000)
287 #define	UMEMB8600(i)	(0x22100000+(i)*0x40000)
288 #endif
289 
290 /*
291  * Macro to offset a UNIBUS device address, often expressed as
292  * something like 0172520, by forcing it into the last 8K
293  * of UNIBUS memory space.
294  */
295 #define	ubdevreg(addr)	((addr) & 017777)
296