1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25 #include <linux/firmware.h>
26 #include <drm/drmP.h>
27 #include "radeon.h"
28 #include "radeon_asic.h"
29 #include "rv770d.h"
30
31 /**
32 * uvd_v2_2_fence_emit - emit an fence & trap command
33 *
34 * @rdev: radeon_device pointer
35 * @fence: fence to emit
36 *
37 * Write a fence and a trap command to the ring.
38 */
uvd_v2_2_fence_emit(struct radeon_device * rdev,struct radeon_fence * fence)39 void uvd_v2_2_fence_emit(struct radeon_device *rdev,
40 struct radeon_fence *fence)
41 {
42 struct radeon_ring *ring = &rdev->ring[fence->ring];
43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
44
45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
46 radeon_ring_write(ring, fence->seq);
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
48 radeon_ring_write(ring, lower_32_bits(addr));
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
52 radeon_ring_write(ring, 0);
53
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
55 radeon_ring_write(ring, 0);
56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
57 radeon_ring_write(ring, 0);
58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
59 radeon_ring_write(ring, 2);
60 }
61
62 /**
63 * uvd_v2_2_semaphore_emit - emit semaphore command
64 *
65 * @rdev: radeon_device pointer
66 * @ring: radeon_ring pointer
67 * @semaphore: semaphore to emit commands for
68 * @emit_wait: true if we should emit a wait command
69 *
70 * Emit a semaphore command (either wait or signal) to the UVD ring.
71 */
uvd_v2_2_semaphore_emit(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_semaphore * semaphore,bool emit_wait)72 bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
73 struct radeon_ring *ring,
74 struct radeon_semaphore *semaphore,
75 bool emit_wait)
76 {
77 uint64_t addr = semaphore->gpu_addr;
78
79 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
80 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
81
82 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
83 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
84
85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
86 radeon_ring_write(ring, emit_wait ? 1 : 0);
87
88 return true;
89 }
90
91 /**
92 * uvd_v2_2_resume - memory controller programming
93 *
94 * @rdev: radeon_device pointer
95 *
96 * Let the UVD memory controller know it's offsets
97 */
uvd_v2_2_resume(struct radeon_device * rdev)98 int uvd_v2_2_resume(struct radeon_device *rdev)
99 {
100 uint64_t addr;
101 uint32_t chip_id, size;
102 int r;
103
104 /* RV770 uses V1.0 MC */
105 if (rdev->family == CHIP_RV770)
106 return uvd_v1_0_resume(rdev);
107
108 r = radeon_uvd_resume(rdev);
109 if (r)
110 return r;
111
112 /* programm the VCPU memory controller bits 0-27 */
113 addr = rdev->uvd.gpu_addr >> 3;
114 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 4) >> 3;
115 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
116 WREG32(UVD_VCPU_CACHE_SIZE0, size);
117
118 addr += size;
119 size = RADEON_UVD_HEAP_SIZE >> 3;
120 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
121 WREG32(UVD_VCPU_CACHE_SIZE1, size);
122
123 addr += size;
124 size = (RADEON_UVD_STACK_SIZE +
125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
126 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
127 WREG32(UVD_VCPU_CACHE_SIZE2, size);
128
129 /* bits 28-31 */
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
131 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
132
133 /* bits 32-39 */
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
135 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
136
137 /* tell firmware which hardware it is running on */
138 switch (rdev->family) {
139 default:
140 return -EINVAL;
141 case CHIP_RV710:
142 chip_id = 0x01000005;
143 break;
144 case CHIP_RV730:
145 chip_id = 0x01000006;
146 break;
147 case CHIP_RV740:
148 chip_id = 0x01000007;
149 break;
150 case CHIP_CYPRESS:
151 case CHIP_HEMLOCK:
152 chip_id = 0x01000008;
153 break;
154 case CHIP_JUNIPER:
155 chip_id = 0x01000009;
156 break;
157 case CHIP_REDWOOD:
158 chip_id = 0x0100000a;
159 break;
160 case CHIP_CEDAR:
161 chip_id = 0x0100000b;
162 break;
163 case CHIP_SUMO:
164 case CHIP_SUMO2:
165 chip_id = 0x0100000c;
166 break;
167 case CHIP_PALM:
168 chip_id = 0x0100000e;
169 break;
170 case CHIP_CAYMAN:
171 chip_id = 0x0100000f;
172 break;
173 case CHIP_BARTS:
174 chip_id = 0x01000010;
175 break;
176 case CHIP_TURKS:
177 chip_id = 0x01000011;
178 break;
179 case CHIP_CAICOS:
180 chip_id = 0x01000012;
181 break;
182 case CHIP_TAHITI:
183 chip_id = 0x01000014;
184 break;
185 case CHIP_VERDE:
186 chip_id = 0x01000015;
187 break;
188 case CHIP_PITCAIRN:
189 case CHIP_OLAND:
190 chip_id = 0x01000016;
191 break;
192 case CHIP_ARUBA:
193 chip_id = 0x01000017;
194 break;
195 }
196 WREG32(UVD_VCPU_CHIP_ID, chip_id);
197
198 return 0;
199 }
200