1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
5 *
6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
7 * under sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include "opt_acpi.h"
32 #if defined(__amd64__)
33 #define DEV_APIC
34 #else
35 #include "opt_apic.h"
36 #endif
37 #include "opt_ddb.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/kernel.h>
42 #include <sys/lock.h>
43 #include <sys/malloc.h>
44 #include <sys/memdesc.h>
45 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/rman.h>
48 #include <sys/rwlock.h>
49 #include <sys/smp.h>
50 #include <sys/taskqueue.h>
51 #include <sys/tree.h>
52 #include <sys/vmem.h>
53 #include <vm/vm.h>
54 #include <vm/vm_extern.h>
55 #include <vm/vm_kern.h>
56 #include <vm/vm_object.h>
57 #include <vm/vm_page.h>
58 #include <vm/vm_pager.h>
59 #include <vm/vm_map.h>
60 #include <contrib/dev/acpica/include/acpi.h>
61 #include <contrib/dev/acpica/include/accommon.h>
62 #include <dev/acpica/acpivar.h>
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <machine/bus.h>
66 #include <machine/pci_cfgreg.h>
67 #include <x86/include/busdma_impl.h>
68 #include <dev/iommu/busdma_iommu.h>
69 #include <x86/iommu/intel_reg.h>
70 #include <x86/iommu/intel_dmar.h>
71
72 #ifdef DEV_APIC
73 #include "pcib_if.h"
74 #include <machine/intr_machdep.h>
75 #include <x86/apicreg.h>
76 #include <x86/apicvar.h>
77 #endif
78
79 #define DMAR_FAULT_IRQ_RID 0
80 #define DMAR_QI_IRQ_RID 1
81 #define DMAR_REG_RID 2
82
83 static device_t *dmar_devs;
84 static int dmar_devcnt;
85
86 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
87
88 static void
dmar_iterate_tbl(dmar_iter_t iter,void * arg)89 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
90 {
91 ACPI_TABLE_DMAR *dmartbl;
92 ACPI_DMAR_HEADER *dmarh;
93 char *ptr, *ptrend;
94 ACPI_STATUS status;
95
96 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
97 if (ACPI_FAILURE(status))
98 return;
99 ptr = (char *)dmartbl + sizeof(*dmartbl);
100 ptrend = (char *)dmartbl + dmartbl->Header.Length;
101 for (;;) {
102 if (ptr >= ptrend)
103 break;
104 dmarh = (ACPI_DMAR_HEADER *)ptr;
105 if (dmarh->Length <= 0) {
106 printf("dmar_identify: corrupted DMAR table, l %d\n",
107 dmarh->Length);
108 break;
109 }
110 ptr += dmarh->Length;
111 if (!iter(dmarh, arg))
112 break;
113 }
114 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
115 }
116
117 struct find_iter_args {
118 int i;
119 ACPI_DMAR_HARDWARE_UNIT *res;
120 };
121
122 static int
dmar_find_iter(ACPI_DMAR_HEADER * dmarh,void * arg)123 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
124 {
125 struct find_iter_args *fia;
126
127 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
128 return (1);
129
130 fia = arg;
131 if (fia->i == 0) {
132 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
133 return (0);
134 }
135 fia->i--;
136 return (1);
137 }
138
139 static ACPI_DMAR_HARDWARE_UNIT *
dmar_find_by_index(int idx)140 dmar_find_by_index(int idx)
141 {
142 struct find_iter_args fia;
143
144 fia.i = idx;
145 fia.res = NULL;
146 dmar_iterate_tbl(dmar_find_iter, &fia);
147 return (fia.res);
148 }
149
150 static int
dmar_count_iter(ACPI_DMAR_HEADER * dmarh,void * arg)151 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
152 {
153
154 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
155 dmar_devcnt++;
156 return (1);
157 }
158
159 int dmar_rmrr_enable = 1;
160
161 static int dmar_enable = 0;
162 static void
dmar_identify(driver_t * driver,device_t parent)163 dmar_identify(driver_t *driver, device_t parent)
164 {
165 ACPI_TABLE_DMAR *dmartbl;
166 ACPI_DMAR_HARDWARE_UNIT *dmarh;
167 ACPI_STATUS status;
168 int i, error;
169
170 if (acpi_disabled("dmar"))
171 return;
172 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
173 if (!dmar_enable)
174 return;
175 TUNABLE_INT_FETCH("hw.dmar.rmrr_enable", &dmar_rmrr_enable);
176
177 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
178 if (ACPI_FAILURE(status))
179 return;
180 haw = dmartbl->Width + 1;
181 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
182 dmar_high = BUS_SPACE_MAXADDR;
183 else
184 dmar_high = 1ULL << (haw + 1);
185 if (bootverbose) {
186 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
187 (unsigned)dmartbl->Flags,
188 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
189 }
190 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
191
192 dmar_iterate_tbl(dmar_count_iter, NULL);
193 if (dmar_devcnt == 0)
194 return;
195 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
196 M_WAITOK | M_ZERO);
197 for (i = 0; i < dmar_devcnt; i++) {
198 dmarh = dmar_find_by_index(i);
199 if (dmarh == NULL) {
200 printf("dmar_identify: cannot find HWUNIT %d\n", i);
201 continue;
202 }
203 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
204 if (dmar_devs[i] == NULL) {
205 printf("dmar_identify: cannot create instance %d\n", i);
206 continue;
207 }
208 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
209 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
210 if (error != 0) {
211 printf(
212 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
213 i, (uintmax_t)dmarh->Address, error);
214 device_delete_child(parent, dmar_devs[i]);
215 dmar_devs[i] = NULL;
216 }
217 }
218 }
219
220 static int
dmar_probe(device_t dev)221 dmar_probe(device_t dev)
222 {
223
224 if (acpi_get_handle(dev) != NULL)
225 return (ENXIO);
226 device_set_desc(dev, "DMA remap");
227 return (BUS_PROBE_NOWILDCARD);
228 }
229
230 static void
dmar_release_intr(device_t dev,struct dmar_unit * unit,int idx)231 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
232 {
233 struct dmar_msi_data *dmd;
234
235 dmd = &unit->intrs[idx];
236 if (dmd->irq == -1)
237 return;
238 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
239 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
240 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
241 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
242 dev, dmd->irq);
243 dmd->irq = -1;
244 }
245
246 static void
dmar_release_resources(device_t dev,struct dmar_unit * unit)247 dmar_release_resources(device_t dev, struct dmar_unit *unit)
248 {
249 int i;
250
251 iommu_fini_busdma(&unit->iommu);
252 dmar_fini_irt(unit);
253 dmar_fini_qi(unit);
254 dmar_fini_fault_log(unit);
255 for (i = 0; i < DMAR_INTR_TOTAL; i++)
256 dmar_release_intr(dev, unit, i);
257 if (unit->regs != NULL) {
258 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
259 unit->regs);
260 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
261 unit->regs);
262 unit->regs = NULL;
263 }
264 if (unit->domids != NULL) {
265 delete_unrhdr(unit->domids);
266 unit->domids = NULL;
267 }
268 if (unit->ctx_obj != NULL) {
269 vm_object_deallocate(unit->ctx_obj);
270 unit->ctx_obj = NULL;
271 }
272 }
273
274 static int
dmar_alloc_irq(device_t dev,struct dmar_unit * unit,int idx)275 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
276 {
277 device_t pcib;
278 struct dmar_msi_data *dmd;
279 uint64_t msi_addr;
280 uint32_t msi_data;
281 int error;
282
283 dmd = &unit->intrs[idx];
284 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
285 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
286 if (error != 0) {
287 device_printf(dev, "cannot allocate %s interrupt, %d\n",
288 dmd->name, error);
289 goto err1;
290 }
291 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
292 dmd->irq, 1);
293 if (error != 0) {
294 device_printf(dev, "cannot set %s interrupt resource, %d\n",
295 dmd->name, error);
296 goto err2;
297 }
298 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
299 &dmd->irq_rid, RF_ACTIVE);
300 if (dmd->irq_res == NULL) {
301 device_printf(dev,
302 "cannot allocate resource for %s interrupt\n", dmd->name);
303 error = ENXIO;
304 goto err3;
305 }
306 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
307 dmd->handler, NULL, unit, &dmd->intr_handle);
308 if (error != 0) {
309 device_printf(dev, "cannot setup %s interrupt, %d\n",
310 dmd->name, error);
311 goto err4;
312 }
313 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
314 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
315 if (error != 0) {
316 device_printf(dev, "cannot map %s interrupt, %d\n",
317 dmd->name, error);
318 goto err5;
319 }
320 dmar_write4(unit, dmd->msi_data_reg, msi_data);
321 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
322 /* Only for xAPIC mode */
323 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
324 return (0);
325
326 err5:
327 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
328 err4:
329 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
330 err3:
331 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
332 err2:
333 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
334 dmd->irq = -1;
335 err1:
336 return (error);
337 }
338
339 #ifdef DEV_APIC
340 static int
dmar_remap_intr(device_t dev,device_t child,u_int irq)341 dmar_remap_intr(device_t dev, device_t child, u_int irq)
342 {
343 struct dmar_unit *unit;
344 struct dmar_msi_data *dmd;
345 uint64_t msi_addr;
346 uint32_t msi_data;
347 int i, error;
348
349 unit = device_get_softc(dev);
350 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
351 dmd = &unit->intrs[i];
352 if (irq == dmd->irq) {
353 error = PCIB_MAP_MSI(device_get_parent(
354 device_get_parent(dev)),
355 dev, irq, &msi_addr, &msi_data);
356 if (error != 0)
357 return (error);
358 DMAR_LOCK(unit);
359 (dmd->disable_intr)(unit);
360 dmar_write4(unit, dmd->msi_data_reg, msi_data);
361 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
362 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
363 (dmd->enable_intr)(unit);
364 DMAR_UNLOCK(unit);
365 return (0);
366 }
367 }
368 return (ENOENT);
369 }
370 #endif
371
372 static void
dmar_print_caps(device_t dev,struct dmar_unit * unit,ACPI_DMAR_HARDWARE_UNIT * dmaru)373 dmar_print_caps(device_t dev, struct dmar_unit *unit,
374 ACPI_DMAR_HARDWARE_UNIT *dmaru)
375 {
376 uint32_t caphi, ecaphi;
377
378 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
379 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
380 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
381 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
382 caphi = unit->hw_cap >> 32;
383 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
384 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
385 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
386 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
387 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
388 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
389 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
390 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
391 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
392 printf("\n");
393 ecaphi = unit->hw_ecap >> 32;
394 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
395 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
396 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
397 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
398 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
399 DMAR_ECAP_IRO(unit->hw_ecap));
400 }
401
402 static int
dmar_attach(device_t dev)403 dmar_attach(device_t dev)
404 {
405 struct dmar_unit *unit;
406 ACPI_DMAR_HARDWARE_UNIT *dmaru;
407 uint64_t timeout;
408 int disable_pmr;
409 int i, error;
410
411 unit = device_get_softc(dev);
412 unit->dev = dev;
413 unit->iommu.unit = device_get_unit(dev);
414 unit->iommu.dev = dev;
415 dmaru = dmar_find_by_index(unit->iommu.unit);
416 if (dmaru == NULL)
417 return (EINVAL);
418 unit->segment = dmaru->Segment;
419 unit->base = dmaru->Address;
420 unit->reg_rid = DMAR_REG_RID;
421 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
422 &unit->reg_rid, RF_ACTIVE);
423 if (unit->regs == NULL) {
424 device_printf(dev, "cannot allocate register window\n");
425 return (ENOMEM);
426 }
427 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
428 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
429 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
430 if (bootverbose)
431 dmar_print_caps(dev, unit, dmaru);
432 dmar_quirks_post_ident(unit);
433
434 timeout = dmar_get_timeout();
435 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout);
436 dmar_update_timeout(timeout);
437
438 for (i = 0; i < DMAR_INTR_TOTAL; i++)
439 unit->intrs[i].irq = -1;
440
441 unit->intrs[DMAR_INTR_FAULT].name = "fault";
442 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
443 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
444 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
445 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
446 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
447 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
448 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
449 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
450 if (error != 0) {
451 dmar_release_resources(dev, unit);
452 return (error);
453 }
454 if (DMAR_HAS_QI(unit)) {
455 unit->intrs[DMAR_INTR_QI].name = "qi";
456 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
457 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
458 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
459 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
460 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
461 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
462 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
463 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
464 if (error != 0) {
465 dmar_release_resources(dev, unit);
466 return (error);
467 }
468 }
469
470 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF);
471 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
472 &unit->iommu.lock);
473 LIST_INIT(&unit->domains);
474
475 /*
476 * 9.2 "Context Entry":
477 * When Caching Mode (CM) field is reported as Set, the
478 * domain-id value of zero is architecturally reserved.
479 * Software must not use domain-id value of zero
480 * when CM is Set.
481 */
482 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
483 alloc_unr_specific(unit->domids, 0);
484
485 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
486 DMAR_CTX_CNT), 0, 0, NULL);
487
488 /*
489 * Allocate and load the root entry table pointer. Enable the
490 * address translation after the required invalidations are
491 * done.
492 */
493 dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO);
494 DMAR_LOCK(unit);
495 error = dmar_load_root_entry_ptr(unit);
496 if (error != 0) {
497 DMAR_UNLOCK(unit);
498 dmar_release_resources(dev, unit);
499 return (error);
500 }
501 error = dmar_inv_ctx_glob(unit);
502 if (error != 0) {
503 DMAR_UNLOCK(unit);
504 dmar_release_resources(dev, unit);
505 return (error);
506 }
507 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
508 error = dmar_inv_iotlb_glob(unit);
509 if (error != 0) {
510 DMAR_UNLOCK(unit);
511 dmar_release_resources(dev, unit);
512 return (error);
513 }
514 }
515
516 DMAR_UNLOCK(unit);
517 error = dmar_init_fault_log(unit);
518 if (error != 0) {
519 dmar_release_resources(dev, unit);
520 return (error);
521 }
522 error = dmar_init_qi(unit);
523 if (error != 0) {
524 dmar_release_resources(dev, unit);
525 return (error);
526 }
527 error = dmar_init_irt(unit);
528 if (error != 0) {
529 dmar_release_resources(dev, unit);
530 return (error);
531 }
532
533 disable_pmr = 0;
534 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr);
535 if (disable_pmr) {
536 error = dmar_disable_protected_regions(unit);
537 if (error != 0)
538 device_printf(dev,
539 "Failed to disable protected regions\n");
540 }
541
542 error = iommu_init_busdma(&unit->iommu);
543 if (error != 0) {
544 dmar_release_resources(dev, unit);
545 return (error);
546 }
547
548 #ifdef NOTYET
549 DMAR_LOCK(unit);
550 error = dmar_enable_translation(unit);
551 if (error != 0) {
552 DMAR_UNLOCK(unit);
553 dmar_release_resources(dev, unit);
554 return (error);
555 }
556 DMAR_UNLOCK(unit);
557 #endif
558
559 return (0);
560 }
561
562 static int
dmar_detach(device_t dev)563 dmar_detach(device_t dev)
564 {
565
566 return (EBUSY);
567 }
568
569 static int
dmar_suspend(device_t dev)570 dmar_suspend(device_t dev)
571 {
572
573 return (0);
574 }
575
576 static int
dmar_resume(device_t dev)577 dmar_resume(device_t dev)
578 {
579
580 /* XXXKIB */
581 return (0);
582 }
583
584 static device_method_t dmar_methods[] = {
585 DEVMETHOD(device_identify, dmar_identify),
586 DEVMETHOD(device_probe, dmar_probe),
587 DEVMETHOD(device_attach, dmar_attach),
588 DEVMETHOD(device_detach, dmar_detach),
589 DEVMETHOD(device_suspend, dmar_suspend),
590 DEVMETHOD(device_resume, dmar_resume),
591 #ifdef DEV_APIC
592 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
593 #endif
594 DEVMETHOD_END
595 };
596
597 static driver_t dmar_driver = {
598 "dmar",
599 dmar_methods,
600 sizeof(struct dmar_unit),
601 };
602
603 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0);
604 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
605
606 static void
dmar_print_path(int busno,int depth,const ACPI_DMAR_PCI_PATH * path)607 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
608 {
609 int i;
610
611 printf("[%d, ", busno);
612 for (i = 0; i < depth; i++) {
613 if (i != 0)
614 printf(", ");
615 printf("(%d, %d)", path[i].Device, path[i].Function);
616 }
617 printf("]");
618 }
619
620 int
dmar_dev_depth(device_t child)621 dmar_dev_depth(device_t child)
622 {
623 devclass_t pci_class;
624 device_t bus, pcib;
625 int depth;
626
627 pci_class = devclass_find("pci");
628 for (depth = 1; ; depth++) {
629 bus = device_get_parent(child);
630 pcib = device_get_parent(bus);
631 if (device_get_devclass(device_get_parent(pcib)) !=
632 pci_class)
633 return (depth);
634 child = pcib;
635 }
636 }
637
638 void
dmar_dev_path(device_t child,int * busno,void * path1,int depth)639 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
640 {
641 devclass_t pci_class;
642 device_t bus, pcib;
643 ACPI_DMAR_PCI_PATH *path;
644
645 pci_class = devclass_find("pci");
646 path = path1;
647 for (depth--; depth != -1; depth--) {
648 path[depth].Device = pci_get_slot(child);
649 path[depth].Function = pci_get_function(child);
650 bus = device_get_parent(child);
651 pcib = device_get_parent(bus);
652 if (device_get_devclass(device_get_parent(pcib)) !=
653 pci_class) {
654 /* reached a host bridge */
655 *busno = pcib_get_bus(bus);
656 return;
657 }
658 child = pcib;
659 }
660 panic("wrong depth");
661 }
662
663 static int
dmar_match_pathes(int busno1,const ACPI_DMAR_PCI_PATH * path1,int depth1,int busno2,const ACPI_DMAR_PCI_PATH * path2,int depth2,enum AcpiDmarScopeType scope_type)664 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
665 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
666 enum AcpiDmarScopeType scope_type)
667 {
668 int i, depth;
669
670 if (busno1 != busno2)
671 return (0);
672 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
673 return (0);
674 depth = depth1;
675 if (depth2 < depth)
676 depth = depth2;
677 for (i = 0; i < depth; i++) {
678 if (path1[i].Device != path2[i].Device ||
679 path1[i].Function != path2[i].Function)
680 return (0);
681 }
682 return (1);
683 }
684
685 static int
dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE * devscope,int dev_busno,const ACPI_DMAR_PCI_PATH * dev_path,int dev_path_len)686 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
687 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
688 {
689 ACPI_DMAR_PCI_PATH *path;
690 int path_len;
691
692 if (devscope->Length < sizeof(*devscope)) {
693 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
694 devscope->Length);
695 return (-1);
696 }
697 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
698 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
699 return (0);
700 path_len = devscope->Length - sizeof(*devscope);
701 if (path_len % 2 != 0) {
702 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
703 devscope->Length);
704 return (-1);
705 }
706 path_len /= 2;
707 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
708 if (path_len == 0) {
709 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
710 devscope->Length);
711 return (-1);
712 }
713
714 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
715 dev_path, dev_path_len, devscope->EntryType));
716 }
717
718 static bool
dmar_match_by_path(struct dmar_unit * unit,int dev_domain,int dev_busno,const ACPI_DMAR_PCI_PATH * dev_path,int dev_path_len,const char ** banner)719 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
720 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
721 {
722 ACPI_DMAR_HARDWARE_UNIT *dmarh;
723 ACPI_DMAR_DEVICE_SCOPE *devscope;
724 char *ptr, *ptrend;
725 int match;
726
727 dmarh = dmar_find_by_index(unit->iommu.unit);
728 if (dmarh == NULL)
729 return (false);
730 if (dmarh->Segment != dev_domain)
731 return (false);
732 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
733 if (banner != NULL)
734 *banner = "INCLUDE_ALL";
735 return (true);
736 }
737 ptr = (char *)dmarh + sizeof(*dmarh);
738 ptrend = (char *)dmarh + dmarh->Header.Length;
739 while (ptr < ptrend) {
740 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
741 ptr += devscope->Length;
742 match = dmar_match_devscope(devscope, dev_busno, dev_path,
743 dev_path_len);
744 if (match == -1)
745 return (false);
746 if (match == 1) {
747 if (banner != NULL)
748 *banner = "specific match";
749 return (true);
750 }
751 }
752 return (false);
753 }
754
755 static struct dmar_unit *
dmar_find_by_scope(int dev_domain,int dev_busno,const ACPI_DMAR_PCI_PATH * dev_path,int dev_path_len)756 dmar_find_by_scope(int dev_domain, int dev_busno,
757 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
758 {
759 struct dmar_unit *unit;
760 int i;
761
762 for (i = 0; i < dmar_devcnt; i++) {
763 if (dmar_devs[i] == NULL)
764 continue;
765 unit = device_get_softc(dmar_devs[i]);
766 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
767 dev_path_len, NULL))
768 return (unit);
769 }
770 return (NULL);
771 }
772
773 struct dmar_unit *
dmar_find(device_t dev,bool verbose)774 dmar_find(device_t dev, bool verbose)
775 {
776 struct dmar_unit *unit;
777 const char *banner;
778 int i, dev_domain, dev_busno, dev_path_len;
779
780 /*
781 * This function can only handle PCI(e) devices.
782 */
783 if (device_get_devclass(device_get_parent(dev)) !=
784 devclass_find("pci"))
785 return (NULL);
786
787 dev_domain = pci_get_domain(dev);
788 dev_path_len = dmar_dev_depth(dev);
789 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
790 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
791 banner = "";
792
793 for (i = 0; i < dmar_devcnt; i++) {
794 if (dmar_devs[i] == NULL)
795 continue;
796 unit = device_get_softc(dmar_devs[i]);
797 if (dmar_match_by_path(unit, dev_domain, dev_busno,
798 dev_path, dev_path_len, &banner))
799 break;
800 }
801 if (i == dmar_devcnt)
802 return (NULL);
803
804 if (verbose) {
805 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
806 dev_domain, pci_get_bus(dev), pci_get_slot(dev),
807 pci_get_function(dev), unit->iommu.unit, banner);
808 printf(" scope path ");
809 dmar_print_path(dev_busno, dev_path_len, dev_path);
810 printf("\n");
811 }
812 return (unit);
813 }
814
815 static struct dmar_unit *
dmar_find_nonpci(u_int id,u_int entry_type,uint16_t * rid)816 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
817 {
818 device_t dmar_dev;
819 struct dmar_unit *unit;
820 ACPI_DMAR_HARDWARE_UNIT *dmarh;
821 ACPI_DMAR_DEVICE_SCOPE *devscope;
822 ACPI_DMAR_PCI_PATH *path;
823 char *ptr, *ptrend;
824 #ifdef DEV_APIC
825 int error;
826 #endif
827 int i;
828
829 for (i = 0; i < dmar_devcnt; i++) {
830 dmar_dev = dmar_devs[i];
831 if (dmar_dev == NULL)
832 continue;
833 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
834 dmarh = dmar_find_by_index(i);
835 if (dmarh == NULL)
836 continue;
837 ptr = (char *)dmarh + sizeof(*dmarh);
838 ptrend = (char *)dmarh + dmarh->Header.Length;
839 for (;;) {
840 if (ptr >= ptrend)
841 break;
842 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
843 ptr += devscope->Length;
844 if (devscope->EntryType != entry_type)
845 continue;
846 if (devscope->EnumerationId != id)
847 continue;
848 #ifdef DEV_APIC
849 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
850 error = ioapic_get_rid(id, rid);
851 /*
852 * If our IOAPIC has PCI bindings then
853 * use the PCI device rid.
854 */
855 if (error == 0)
856 return (unit);
857 }
858 #endif
859 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
860 == 2) {
861 if (rid != NULL) {
862 path = (ACPI_DMAR_PCI_PATH *)
863 (devscope + 1);
864 *rid = PCI_RID(devscope->Bus,
865 path->Device, path->Function);
866 }
867 return (unit);
868 }
869 printf(
870 "dmar_find_nonpci: id %d type %d path length != 2\n",
871 id, entry_type);
872 break;
873 }
874 }
875 return (NULL);
876 }
877
878 struct dmar_unit *
dmar_find_hpet(device_t dev,uint16_t * rid)879 dmar_find_hpet(device_t dev, uint16_t *rid)
880 {
881
882 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
883 rid));
884 }
885
886 struct dmar_unit *
dmar_find_ioapic(u_int apic_id,uint16_t * rid)887 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
888 {
889
890 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
891 }
892
893 struct rmrr_iter_args {
894 struct dmar_domain *domain;
895 int dev_domain;
896 int dev_busno;
897 const ACPI_DMAR_PCI_PATH *dev_path;
898 int dev_path_len;
899 struct iommu_map_entries_tailq *rmrr_entries;
900 };
901
902 static int
dmar_rmrr_iter(ACPI_DMAR_HEADER * dmarh,void * arg)903 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
904 {
905 struct rmrr_iter_args *ria;
906 ACPI_DMAR_RESERVED_MEMORY *resmem;
907 ACPI_DMAR_DEVICE_SCOPE *devscope;
908 struct iommu_map_entry *entry;
909 char *ptr, *ptrend;
910 int match;
911
912 if (!dmar_rmrr_enable)
913 return (1);
914
915 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
916 return (1);
917
918 ria = arg;
919 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
920 if (resmem->Segment != ria->dev_domain)
921 return (1);
922
923 ptr = (char *)resmem + sizeof(*resmem);
924 ptrend = (char *)resmem + resmem->Header.Length;
925 for (;;) {
926 if (ptr >= ptrend)
927 break;
928 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
929 ptr += devscope->Length;
930 match = dmar_match_devscope(devscope, ria->dev_busno,
931 ria->dev_path, ria->dev_path_len);
932 if (match == 1) {
933 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain),
934 IOMMU_PGF_WAITOK);
935 entry->start = resmem->BaseAddress;
936 /* The RMRR entry end address is inclusive. */
937 entry->end = resmem->EndAddress;
938 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
939 dmamap_link);
940 }
941 }
942
943 return (1);
944 }
945
946 void
dmar_dev_parse_rmrr(struct dmar_domain * domain,int dev_domain,int dev_busno,const void * dev_path,int dev_path_len,struct iommu_map_entries_tailq * rmrr_entries)947 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
948 const void *dev_path, int dev_path_len,
949 struct iommu_map_entries_tailq *rmrr_entries)
950 {
951 struct rmrr_iter_args ria;
952
953 ria.domain = domain;
954 ria.dev_domain = dev_domain;
955 ria.dev_busno = dev_busno;
956 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
957 ria.dev_path_len = dev_path_len;
958 ria.rmrr_entries = rmrr_entries;
959 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
960 }
961
962 struct inst_rmrr_iter_args {
963 struct dmar_unit *dmar;
964 };
965
966 static device_t
dmar_path_dev(int segment,int path_len,int busno,const ACPI_DMAR_PCI_PATH * path,uint16_t * rid)967 dmar_path_dev(int segment, int path_len, int busno,
968 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
969 {
970 device_t dev;
971 int i;
972
973 dev = NULL;
974 for (i = 0; i < path_len; i++) {
975 dev = pci_find_dbsf(segment, busno, path->Device,
976 path->Function);
977 if (i != path_len - 1) {
978 busno = pci_cfgregread(segment, busno, path->Device,
979 path->Function, PCIR_SECBUS_1, 1);
980 path++;
981 }
982 }
983 *rid = PCI_RID(busno, path->Device, path->Function);
984 return (dev);
985 }
986
987 static int
dmar_inst_rmrr_iter(ACPI_DMAR_HEADER * dmarh,void * arg)988 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
989 {
990 const ACPI_DMAR_RESERVED_MEMORY *resmem;
991 const ACPI_DMAR_DEVICE_SCOPE *devscope;
992 struct inst_rmrr_iter_args *iria;
993 const char *ptr, *ptrend;
994 device_t dev;
995 struct dmar_unit *unit;
996 int dev_path_len;
997 uint16_t rid;
998
999 iria = arg;
1000
1001 if (!dmar_rmrr_enable)
1002 return (1);
1003
1004 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
1005 return (1);
1006
1007 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
1008 if (resmem->Segment != iria->dmar->segment)
1009 return (1);
1010
1011 ptr = (const char *)resmem + sizeof(*resmem);
1012 ptrend = (const char *)resmem + resmem->Header.Length;
1013 for (;;) {
1014 if (ptr >= ptrend)
1015 break;
1016 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
1017 ptr += devscope->Length;
1018 /* XXXKIB bridge */
1019 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
1020 continue;
1021 rid = 0;
1022 dev_path_len = (devscope->Length -
1023 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
1024 dev = dmar_path_dev(resmem->Segment, dev_path_len,
1025 devscope->Bus,
1026 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
1027 if (dev == NULL) {
1028 if (bootverbose) {
1029 printf("dmar%d no dev found for RMRR "
1030 "[%#jx, %#jx] rid %#x scope path ",
1031 iria->dmar->iommu.unit,
1032 (uintmax_t)resmem->BaseAddress,
1033 (uintmax_t)resmem->EndAddress,
1034 rid);
1035 dmar_print_path(devscope->Bus, dev_path_len,
1036 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1037 printf("\n");
1038 }
1039 unit = dmar_find_by_scope(resmem->Segment,
1040 devscope->Bus,
1041 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1042 dev_path_len);
1043 if (iria->dmar != unit)
1044 continue;
1045 dmar_get_ctx_for_devpath(iria->dmar, rid,
1046 resmem->Segment, devscope->Bus,
1047 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1048 dev_path_len, false, true);
1049 } else {
1050 unit = dmar_find(dev, false);
1051 if (iria->dmar != unit)
1052 continue;
1053 iommu_instantiate_ctx(&(iria)->dmar->iommu,
1054 dev, true);
1055 }
1056 }
1057
1058 return (1);
1059
1060 }
1061
1062 /*
1063 * Pre-create all contexts for the DMAR which have RMRR entries.
1064 */
1065 int
dmar_instantiate_rmrr_ctxs(struct iommu_unit * unit)1066 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit)
1067 {
1068 struct dmar_unit *dmar;
1069 struct inst_rmrr_iter_args iria;
1070 int error;
1071
1072 dmar = IOMMU2DMAR(unit);
1073
1074 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1075 return (0);
1076
1077 error = 0;
1078 iria.dmar = dmar;
1079 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1080 DMAR_LOCK(dmar);
1081 if (!LIST_EMPTY(&dmar->domains)) {
1082 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1083 ("dmar%d: RMRR not handled but translation is already enabled",
1084 dmar->iommu.unit));
1085 error = dmar_disable_protected_regions(dmar);
1086 if (error != 0)
1087 printf("dmar%d: Failed to disable protected regions\n",
1088 dmar->iommu.unit);
1089 error = dmar_enable_translation(dmar);
1090 if (bootverbose) {
1091 if (error == 0) {
1092 printf("dmar%d: enabled translation\n",
1093 dmar->iommu.unit);
1094 } else {
1095 printf("dmar%d: enabling translation failed, "
1096 "error %d\n", dmar->iommu.unit, error);
1097 }
1098 }
1099 }
1100 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1101 return (error);
1102 }
1103
1104 #ifdef DDB
1105 #include <ddb/ddb.h>
1106 #include <ddb/db_lex.h>
1107
1108 static void
dmar_print_domain_entry(const struct iommu_map_entry * entry)1109 dmar_print_domain_entry(const struct iommu_map_entry *entry)
1110 {
1111 struct iommu_map_entry *l, *r;
1112
1113 db_printf(
1114 " start %jx end %jx first %jx last %jx free_down %jx flags %x ",
1115 entry->start, entry->end, entry->first, entry->last,
1116 entry->free_down, entry->flags);
1117 db_printf("left ");
1118 l = RB_LEFT(entry, rb_entry);
1119 if (l == NULL)
1120 db_printf("NULL ");
1121 else
1122 db_printf("%jx ", l->start);
1123 db_printf("right ");
1124 r = RB_RIGHT(entry, rb_entry);
1125 if (r == NULL)
1126 db_printf("NULL");
1127 else
1128 db_printf("%jx", r->start);
1129 db_printf("\n");
1130 }
1131
1132 static void
dmar_print_ctx(struct dmar_ctx * ctx)1133 dmar_print_ctx(struct dmar_ctx *ctx)
1134 {
1135
1136 db_printf(
1137 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1138 ctx, pci_get_bus(ctx->context.tag->owner),
1139 pci_get_slot(ctx->context.tag->owner),
1140 pci_get_function(ctx->context.tag->owner), ctx->refs,
1141 ctx->context.flags, ctx->context.loads, ctx->context.unloads);
1142 }
1143
1144 static void
dmar_print_domain(struct dmar_domain * domain,bool show_mappings)1145 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1146 {
1147 struct iommu_domain *iodom;
1148 struct iommu_map_entry *entry;
1149 struct dmar_ctx *ctx;
1150
1151 iodom = DOM2IODOM(domain);
1152
1153 db_printf(
1154 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1155 " ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1156 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1157 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt,
1158 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt);
1159 if (!LIST_EMPTY(&domain->contexts)) {
1160 db_printf(" Contexts:\n");
1161 LIST_FOREACH(ctx, &domain->contexts, link)
1162 dmar_print_ctx(ctx);
1163 }
1164 if (!show_mappings)
1165 return;
1166 db_printf(" mapped:\n");
1167 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) {
1168 dmar_print_domain_entry(entry);
1169 if (db_pager_quit)
1170 break;
1171 }
1172 if (db_pager_quit)
1173 return;
1174 db_printf(" unloading:\n");
1175 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) {
1176 dmar_print_domain_entry(entry);
1177 if (db_pager_quit)
1178 break;
1179 }
1180 }
1181
DB_SHOW_COMMAND_FLAGS(dmar_domain,db_dmar_print_domain,CS_OWN)1182 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN)
1183 {
1184 struct dmar_unit *unit;
1185 struct dmar_domain *domain;
1186 struct dmar_ctx *ctx;
1187 bool show_mappings, valid;
1188 int pci_domain, bus, device, function, i, t;
1189 db_expr_t radix;
1190
1191 valid = false;
1192 radix = db_radix;
1193 db_radix = 10;
1194 t = db_read_token();
1195 if (t == tSLASH) {
1196 t = db_read_token();
1197 if (t != tIDENT) {
1198 db_printf("Bad modifier\n");
1199 db_radix = radix;
1200 db_skip_to_eol();
1201 return;
1202 }
1203 show_mappings = strchr(db_tok_string, 'm') != NULL;
1204 t = db_read_token();
1205 } else {
1206 show_mappings = false;
1207 }
1208 if (t == tNUMBER) {
1209 pci_domain = db_tok_number;
1210 t = db_read_token();
1211 if (t == tNUMBER) {
1212 bus = db_tok_number;
1213 t = db_read_token();
1214 if (t == tNUMBER) {
1215 device = db_tok_number;
1216 t = db_read_token();
1217 if (t == tNUMBER) {
1218 function = db_tok_number;
1219 valid = true;
1220 }
1221 }
1222 }
1223 }
1224 db_radix = radix;
1225 db_skip_to_eol();
1226 if (!valid) {
1227 db_printf("usage: show dmar_domain [/m] "
1228 "<domain> <bus> <device> <func>\n");
1229 return;
1230 }
1231 for (i = 0; i < dmar_devcnt; i++) {
1232 unit = device_get_softc(dmar_devs[i]);
1233 LIST_FOREACH(domain, &unit->domains, link) {
1234 LIST_FOREACH(ctx, &domain->contexts, link) {
1235 if (pci_domain == unit->segment &&
1236 bus == pci_get_bus(ctx->context.tag->owner) &&
1237 device ==
1238 pci_get_slot(ctx->context.tag->owner) &&
1239 function ==
1240 pci_get_function(ctx->context.tag->owner)) {
1241 dmar_print_domain(domain,
1242 show_mappings);
1243 goto out;
1244 }
1245 }
1246 }
1247 }
1248 out:;
1249 }
1250
1251 static void
dmar_print_one(int idx,bool show_domains,bool show_mappings)1252 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1253 {
1254 struct dmar_unit *unit;
1255 struct dmar_domain *domain;
1256 int i, frir;
1257
1258 unit = device_get_softc(dmar_devs[idx]);
1259 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit,
1260 unit, dmar_read8(unit, DMAR_RTADDR_REG),
1261 dmar_read4(unit, DMAR_VER_REG));
1262 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1263 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1264 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1265 dmar_read4(unit, DMAR_GSTS_REG),
1266 dmar_read4(unit, DMAR_FSTS_REG),
1267 dmar_read4(unit, DMAR_FECTL_REG));
1268 if (unit->ir_enabled) {
1269 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1270 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1271 }
1272 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1273 dmar_read4(unit, DMAR_FEDATA_REG),
1274 dmar_read4(unit, DMAR_FEADDR_REG),
1275 dmar_read4(unit, DMAR_FEUADDR_REG));
1276 db_printf("primary fault log:\n");
1277 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1278 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1279 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1280 (uintmax_t)dmar_read8(unit, frir),
1281 (uintmax_t)dmar_read8(unit, frir + 8));
1282 }
1283 if (DMAR_HAS_QI(unit)) {
1284 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1285 dmar_read4(unit, DMAR_IEDATA_REG),
1286 dmar_read4(unit, DMAR_IEADDR_REG),
1287 dmar_read4(unit, DMAR_IEUADDR_REG));
1288 if (unit->qi_enabled) {
1289 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1290 "size 0x%jx\n"
1291 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1292 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1293 (uintmax_t)unit->inv_queue,
1294 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1295 (uintmax_t)unit->inv_queue_size,
1296 dmar_read4(unit, DMAR_IQH_REG),
1297 dmar_read4(unit, DMAR_IQT_REG),
1298 unit->inv_queue_avail,
1299 dmar_read4(unit, DMAR_ICS_REG),
1300 dmar_read4(unit, DMAR_IECTL_REG),
1301 unit->inv_waitd_seq_hw,
1302 &unit->inv_waitd_seq_hw,
1303 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1304 unit->inv_waitd_seq,
1305 unit->inv_waitd_gen);
1306 } else {
1307 db_printf("qi is disabled\n");
1308 }
1309 }
1310 if (show_domains) {
1311 db_printf("domains:\n");
1312 LIST_FOREACH(domain, &unit->domains, link) {
1313 dmar_print_domain(domain, show_mappings);
1314 if (db_pager_quit)
1315 break;
1316 }
1317 }
1318 }
1319
DB_SHOW_COMMAND(dmar,db_dmar_print)1320 DB_SHOW_COMMAND(dmar, db_dmar_print)
1321 {
1322 bool show_domains, show_mappings;
1323
1324 show_domains = strchr(modif, 'd') != NULL;
1325 show_mappings = strchr(modif, 'm') != NULL;
1326 if (!have_addr) {
1327 db_printf("usage: show dmar [/d] [/m] index\n");
1328 return;
1329 }
1330 dmar_print_one((int)addr, show_domains, show_mappings);
1331 }
1332
DB_SHOW_ALL_COMMAND(dmars,db_show_all_dmars)1333 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1334 {
1335 int i;
1336 bool show_domains, show_mappings;
1337
1338 show_domains = strchr(modif, 'd') != NULL;
1339 show_mappings = strchr(modif, 'm') != NULL;
1340
1341 for (i = 0; i < dmar_devcnt; i++) {
1342 dmar_print_one(i, show_domains, show_mappings);
1343 if (db_pager_quit)
1344 break;
1345 }
1346 }
1347 #endif
1348
1349 struct iommu_unit *
iommu_find(device_t dev,bool verbose)1350 iommu_find(device_t dev, bool verbose)
1351 {
1352 struct dmar_unit *dmar;
1353
1354 dmar = dmar_find(dev, verbose);
1355
1356 return (&dmar->iommu);
1357 }
1358