1 /*-
2 * Copyright 1998 Massachusetts Institute of Technology
3 *
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
6 * granted, provided that both the above copyright notice and this
7 * permission notice appear in all copies, that both the above
8 * copyright notice and this permission notice appear in all
9 * supporting documentation, and that the name of M.I.T. not be used
10 * in advertising or publicity pertaining to distribution of the
11 * software without specific, written prior permission. M.I.T. makes
12 * no representations about the suitability of this software for any
13 * purpose. It is provided "as is" without express or implied
14 * warranty.
15 *
16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 /*
32 * This code implements a system driver for legacy systems that do not
33 * support ACPI or when ACPI support is not present in the kernel.
34 */
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cpu.h>
40 #include <sys/kernel.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <machine/bus.h>
44 #include <sys/pcpu.h>
45 #include <sys/rman.h>
46 #include <sys/smp.h>
47 #include <dev/pci/pcireg.h>
48
49 #include <machine/clock.h>
50 #include <machine/pci_cfgreg.h>
51 #include <machine/resource.h>
52 #include <x86/legacyvar.h>
53
54 static MALLOC_DEFINE(M_LEGACYDEV, "legacydrv", "legacy system device");
55 struct legacy_device {
56 int lg_pcibus;
57 int lg_pcislot;
58 int lg_pcifunc;
59 };
60
61 #define DEVTOAT(dev) ((struct legacy_device *)device_get_ivars(dev))
62
63 static int legacy_probe(device_t);
64 static int legacy_attach(device_t);
65 static int legacy_print_child(device_t, device_t);
66 static device_t legacy_add_child(device_t bus, u_int order, const char *name,
67 int unit);
68 static int legacy_read_ivar(device_t, device_t, int, uintptr_t *);
69 static int legacy_write_ivar(device_t, device_t, int, uintptr_t);
70
71 static device_method_t legacy_methods[] = {
72 /* Device interface */
73 DEVMETHOD(device_probe, legacy_probe),
74 DEVMETHOD(device_attach, legacy_attach),
75 DEVMETHOD(device_detach, bus_generic_detach),
76 DEVMETHOD(device_shutdown, bus_generic_shutdown),
77 DEVMETHOD(device_suspend, bus_generic_suspend),
78 DEVMETHOD(device_resume, bus_generic_resume),
79
80 /* Bus interface */
81 DEVMETHOD(bus_print_child, legacy_print_child),
82 DEVMETHOD(bus_add_child, legacy_add_child),
83 DEVMETHOD(bus_read_ivar, legacy_read_ivar),
84 DEVMETHOD(bus_write_ivar, legacy_write_ivar),
85 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
86 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
87 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
88 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
89 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
90 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
91 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
92 { 0, 0 }
93 };
94
95 static driver_t legacy_driver = {
96 "legacy",
97 legacy_methods,
98 1, /* no softc */
99 };
100
101 DRIVER_MODULE(legacy, nexus, legacy_driver, 0, 0);
102
103 static int
legacy_probe(device_t dev)104 legacy_probe(device_t dev)
105 {
106
107 device_set_desc(dev, "legacy system");
108 device_quiet(dev);
109 return (0);
110 }
111
112 /*
113 * Grope around in the PCI config space to see if this is a chipset
114 * that is capable of doing memory-mapped config cycles. This also
115 * implies that it can do PCIe extended config cycles.
116 */
117 static void
legacy_pci_cfgregopen(device_t dev)118 legacy_pci_cfgregopen(device_t dev)
119 {
120 uint64_t pciebar;
121 u_int16_t did, vid;
122
123 if (cfgmech == CFGMECH_NONE || cfgmech == CFGMECH_PCIE)
124 return;
125
126 /* Check for supported chipsets */
127 vid = pci_cfgregread(0, 0, 0, 0, PCIR_VENDOR, 2);
128 did = pci_cfgregread(0, 0, 0, 0, PCIR_DEVICE, 2);
129 switch (vid) {
130 case 0x8086:
131 switch (did) {
132 case 0x3590:
133 case 0x3592:
134 /* Intel 7520 or 7320 */
135 pciebar = pci_cfgregread(0, 0, 0, 0, 0xce, 2) << 16;
136 pcie_cfgregopen(pciebar, 0, 0, 255);
137 break;
138 case 0x2580:
139 case 0x2584:
140 case 0x2590:
141 /* Intel 915, 925, or 915GM */
142 pciebar = pci_cfgregread(0, 0, 0, 0, 0x48, 4);
143 pcie_cfgregopen(pciebar, 0, 0, 255);
144 break;
145 }
146 }
147
148 if (bootverbose && cfgmech == CFGMECH_PCIE)
149 device_printf(dev, "Enabled ECAM PCIe accesses\n");
150 }
151
152 static int
legacy_attach(device_t dev)153 legacy_attach(device_t dev)
154 {
155 device_t child;
156
157 legacy_pci_cfgregopen(dev);
158
159 /*
160 * Let our child drivers identify any child devices that they
161 * can find. Once that is done attach any devices that we
162 * found.
163 */
164 bus_generic_probe(dev);
165 bus_generic_attach(dev);
166
167 /*
168 * If we didn't see ISA on a PCI bridge, add a top-level bus.
169 */
170 if (!devclass_get_device(devclass_find("isa"), 0)) {
171 child = BUS_ADD_CHILD(dev, 0, "isa", 0);
172 if (child == NULL)
173 panic("legacy_attach isa");
174 device_probe_and_attach(child);
175 }
176
177 return 0;
178 }
179
180 static int
legacy_print_child(device_t bus,device_t child)181 legacy_print_child(device_t bus, device_t child)
182 {
183 struct legacy_device *atdev = DEVTOAT(child);
184 int retval = 0;
185
186 retval += bus_print_child_header(bus, child);
187 if (atdev->lg_pcibus != -1)
188 retval += printf(" pcibus %d", atdev->lg_pcibus);
189 retval += printf("\n");
190
191 return (retval);
192 }
193
194 static device_t
legacy_add_child(device_t bus,u_int order,const char * name,int unit)195 legacy_add_child(device_t bus, u_int order, const char *name, int unit)
196 {
197 device_t child;
198 struct legacy_device *atdev;
199
200 atdev = malloc(sizeof(struct legacy_device), M_LEGACYDEV,
201 M_NOWAIT | M_ZERO);
202 if (atdev == NULL)
203 return(NULL);
204 atdev->lg_pcibus = -1;
205 atdev->lg_pcislot = -1;
206 atdev->lg_pcifunc = -1;
207
208 child = device_add_child_ordered(bus, order, name, unit);
209 if (child == NULL)
210 free(atdev, M_LEGACYDEV);
211 else
212 /* should we free this in legacy_child_detached? */
213 device_set_ivars(child, atdev);
214
215 return (child);
216 }
217
218 static int
legacy_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)219 legacy_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
220 {
221 struct legacy_device *atdev = DEVTOAT(child);
222
223 switch (which) {
224 case LEGACY_IVAR_PCIDOMAIN:
225 *result = 0;
226 break;
227 case LEGACY_IVAR_PCIBUS:
228 *result = atdev->lg_pcibus;
229 break;
230 case LEGACY_IVAR_PCISLOT:
231 *result = atdev->lg_pcislot;
232 break;
233 case LEGACY_IVAR_PCIFUNC:
234 *result = atdev->lg_pcifunc;
235 break;
236 default:
237 return ENOENT;
238 }
239 return 0;
240 }
241
242 static int
legacy_write_ivar(device_t dev,device_t child,int which,uintptr_t value)243 legacy_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
244 {
245 struct legacy_device *atdev = DEVTOAT(child);
246
247 switch (which) {
248 case LEGACY_IVAR_PCIDOMAIN:
249 return EINVAL;
250 case LEGACY_IVAR_PCIBUS:
251 atdev->lg_pcibus = value;
252 break;
253 case LEGACY_IVAR_PCISLOT:
254 atdev->lg_pcislot = value;
255 break;
256 case LEGACY_IVAR_PCIFUNC:
257 atdev->lg_pcifunc = value;
258 break;
259 default:
260 return ENOENT;
261 }
262 return 0;
263 }
264
265 /*
266 * Legacy CPU attachment when ACPI is not available. Drivers like
267 * cpufreq(4) hang off this.
268 */
269 static void cpu_identify(driver_t *driver, device_t parent);
270 static int cpu_read_ivar(device_t dev, device_t child, int index,
271 uintptr_t *result);
272 static device_t cpu_add_child(device_t bus, u_int order, const char *name,
273 int unit);
274 static struct resource_list *cpu_get_rlist(device_t dev, device_t child);
275
276 struct cpu_device {
277 struct resource_list cd_rl;
278 struct pcpu *cd_pcpu;
279 };
280
281 static device_method_t cpu_methods[] = {
282 /* Device interface */
283 DEVMETHOD(device_identify, cpu_identify),
284 DEVMETHOD(device_probe, bus_generic_probe),
285 DEVMETHOD(device_attach, bus_generic_attach),
286 DEVMETHOD(device_detach, bus_generic_detach),
287 DEVMETHOD(device_shutdown, bus_generic_shutdown),
288 DEVMETHOD(device_suspend, bus_generic_suspend),
289 DEVMETHOD(device_resume, bus_generic_resume),
290
291 /* Bus interface */
292 DEVMETHOD(bus_add_child, cpu_add_child),
293 DEVMETHOD(bus_read_ivar, cpu_read_ivar),
294 DEVMETHOD(bus_get_resource_list, cpu_get_rlist),
295 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
296 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
297 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
298 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
299 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
300 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
301 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
302 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
303
304 DEVMETHOD_END
305 };
306
307 static driver_t cpu_driver = {
308 "cpu",
309 cpu_methods,
310 1, /* no softc */
311 };
312
313 DRIVER_MODULE(cpu, legacy, cpu_driver, 0, 0);
314
315 static void
cpu_identify(driver_t * driver,device_t parent)316 cpu_identify(driver_t *driver, device_t parent)
317 {
318 device_t child;
319 int i;
320
321 /*
322 * Attach a cpuX device for each CPU. We use an order of 150
323 * so that these devices are attached after the Host-PCI
324 * bridges (which are added at order 100).
325 */
326 CPU_FOREACH(i) {
327 child = BUS_ADD_CHILD(parent, 150, "cpu", i);
328 if (child == NULL)
329 panic("legacy_attach cpu");
330 }
331 }
332
333 static device_t
cpu_add_child(device_t bus,u_int order,const char * name,int unit)334 cpu_add_child(device_t bus, u_int order, const char *name, int unit)
335 {
336 struct cpu_device *cd;
337 device_t child;
338 struct pcpu *pc;
339
340 if ((cd = malloc(sizeof(*cd), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL)
341 return (NULL);
342
343 resource_list_init(&cd->cd_rl);
344 pc = pcpu_find(device_get_unit(bus));
345 cd->cd_pcpu = pc;
346
347 child = device_add_child_ordered(bus, order, name, unit);
348 if (child != NULL) {
349 pc->pc_device = child;
350 device_set_ivars(child, cd);
351 } else
352 free(cd, M_DEVBUF);
353 return (child);
354 }
355
356 static struct resource_list *
cpu_get_rlist(device_t dev,device_t child)357 cpu_get_rlist(device_t dev, device_t child)
358 {
359 struct cpu_device *cpdev;
360
361 cpdev = device_get_ivars(child);
362 return (&cpdev->cd_rl);
363 }
364
365 static int
cpu_read_ivar(device_t dev,device_t child,int index,uintptr_t * result)366 cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
367 {
368 struct cpu_device *cpdev;
369
370 switch (index) {
371 case CPU_IVAR_PCPU:
372 cpdev = device_get_ivars(child);
373 *result = (uintptr_t)cpdev->cd_pcpu;
374 break;
375 case CPU_IVAR_NOMINAL_MHZ:
376 if (tsc_is_invariant) {
377 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) /
378 1000000);
379 break;
380 }
381 /* FALLTHROUGH */
382 default:
383 return (ENOENT);
384 }
385 return (0);
386 }
387