H A D | cells_sim.v | 61 input C, PRE, CLR, D; port 71 else if (PRE == 1) 81 input C, PRE, CLR, D; port 91 else if (PRE == 1) 101 input G, PRE, CLR, D; port 113 else if (PRE == 1) 121 input G, PRE, CLR, D; port 133 else if (PRE == 1) 166 input C, PRE, CLR, D; port 186 input C, PRE, CLR, T; port [all …]
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