ADC_AWD_CR1_REGOFFSET (reference) in projects: dports

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Searched refs:ADC_AWD_CR1_REGOFFSET (Results 1 – 6 of 6) sorted by relevance

/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/
H A D	stm32h7xx_ll_adc.h	`308 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL) macro 317 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET \| ADC_AWD_CR2_REGOFFSET \| ADC_AWD… 326 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) 1113 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /*!<…`
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A D	stm32l1xx_ll_adc.h	`325 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) in make_crc_table() 327 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) in make_crc_table() 1015 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /*!<…`
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A D	stm32l1xx_ll_adc.h	`325 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) macro 327 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 1015 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /*!<…`
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A D	stm32l1xx_ll_adc.h	`325 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) macro 327 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 1015 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /*!<…`
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A D	stm32l1xx_ll_adc.h	`325 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) macro 327 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 1015 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /*!<…`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A D	stm32g4xx_ll_adc.h	`291 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL) macro 300 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET \| ADC_AWD_CR2_REGOFFSET \| ADC_AWD… 309 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) 1243 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /*!<…`