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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir94 ; CHECK: $x10 = ADDI $x0, 50
140 ; CHECK: $x1 = ADDI $x0, 50
184 renamable $x1 = ADDI $x0, 255
186 renamable $x6 = ADDI %stack.0, 384
188 renamable $x10 = ADDI $x0, 128
199 renamable $x25 = ADDI %stack.0, 0
200 renamable $x26 = ADDI %stack.0, 0
201 renamable $x27 = ADDI $x0, 2
202 renamable $x28 = ADDI %stack.0, 640
203 renamable $x29 = ADDI %stack.0, 768
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir94 ; CHECK: $x10 = ADDI $x0, 50
140 ; CHECK: $x1 = ADDI $x0, 50
184 renamable $x1 = ADDI $x0, 255
186 renamable $x6 = ADDI %stack.0, 384
188 renamable $x10 = ADDI $x0, 128
199 renamable $x25 = ADDI %stack.0, 0
200 renamable $x26 = ADDI %stack.0, 0
201 renamable $x27 = ADDI $x0, 2
202 renamable $x28 = ADDI %stack.0, 640
203 renamable $x29 = ADDI %stack.0, 768
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir94 ; CHECK: $x10 = ADDI $x0, 50
140 ; CHECK: $x1 = ADDI $x0, 50
184 renamable $x1 = ADDI $x0, 255
186 renamable $x6 = ADDI %stack.0, 384
188 renamable $x10 = ADDI $x0, 128
199 renamable $x25 = ADDI %stack.0, 0
200 renamable $x26 = ADDI %stack.0, 0
201 renamable $x27 = ADDI $x0, 2
202 renamable $x28 = ADDI %stack.0, 640
203 renamable $x29 = ADDI %stack.0, 768
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir94 ; CHECK: $x10 = ADDI $x0, 50
140 ; CHECK: $x1 = ADDI $x0, 50
184 renamable $x1 = ADDI $x0, 255
186 renamable $x6 = ADDI %stack.0, 384
188 renamable $x10 = ADDI $x0, 128
199 renamable $x25 = ADDI %stack.0, 0
200 renamable $x26 = ADDI %stack.0, 0
201 renamable $x27 = ADDI $x0, 2
202 renamable $x28 = ADDI %stack.0, 640
203 renamable $x29 = ADDI %stack.0, 768
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir94 ; CHECK: $x10 = ADDI $x0, 50
140 ; CHECK: $x1 = ADDI $x0, 50
184 renamable $x1 = ADDI $x0, 255
186 renamable $x6 = ADDI %stack.0, 384
188 renamable $x10 = ADDI $x0, 128
199 renamable $x25 = ADDI %stack.0, 0
200 renamable $x26 = ADDI %stack.0, 0
201 renamable $x27 = ADDI $x0, 2
202 renamable $x28 = ADDI %stack.0, 640
203 renamable $x29 = ADDI %stack.0, 768
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir95 ; CHECK-NEXT: $x10 = ADDI $x0, 50
141 ; CHECK-NEXT: $x1 = ADDI $x0, 50
188 renamable $x1 = ADDI $x0, 255
190 renamable $x6 = ADDI %stack.0, 384
192 renamable $x10 = ADDI $x0, 128
203 renamable $x25 = ADDI %stack.0, 0
204 renamable $x26 = ADDI %stack.0, 0
205 renamable $x27 = ADDI $x0, 2
206 renamable $x28 = ADDI %stack.0, 640
207 renamable $x29 = ADDI %stack.0, 768
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/RISCV/
H A Dvector-abi.ll14 ; RV32: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
15 ; RV32: SW killed [[ADDI]], %stack.0, 12 :: (store (s32) into %stack.0)
16 ; RV32: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
18 ; RV32: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
20 ; RV32: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
22 ; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
34 ; RV64: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
36 ; RV64: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
38 ; RV64: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
40 ; RV64: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
[all …]
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
H A Dmachineoutliner-jumptable.mir25 ; RV32I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
30 ; RV64I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
33 $x12 = ADDI $x10, 17
37 $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
44 $x12 = ADDI $x10, 17
48 $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
55 $x12 = ADDI $x10, 17
59 $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dvector-abi.ll14 ; RV32: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
15 ; RV32: SW killed [[ADDI]], %stack.0, 12 :: (store (s32) into %stack.0)
16 ; RV32: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
18 ; RV32: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
20 ; RV32: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
22 ; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
34 ; RV64: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
36 ; RV64: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
38 ; RV64: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
40 ; RV64: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
[all …]
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/RISCV/
H A Dvector-abi.ll14 ; RV32: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
15 ; RV32: SW killed [[ADDI]], %stack.0, 12 :: (store (s32) into %stack.0)
16 ; RV32: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
18 ; RV32: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
20 ; RV32: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
22 ; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
34 ; RV64: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
36 ; RV64: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
38 ; RV64: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
40 ; RV64: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
[all …]
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dvector-abi.ll14 ; RV32: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
15 ; RV32: SW killed [[ADDI]], %stack.0, 12 :: (store (s32) into %stack.0)
16 ; RV32: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
18 ; RV32: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
20 ; RV32: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
22 ; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
34 ; RV64: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
36 ; RV64: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
38 ; RV64: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
40 ; RV64: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
[all …]
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dvector-abi.ll14 ; RV32: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
15 ; RV32: SW killed [[ADDI]], %stack.0, 12 :: (store (s32) into %stack.0)
16 ; RV32: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
18 ; RV32: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
20 ; RV32: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
22 ; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
34 ; RV64: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 7
36 ; RV64: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 6
38 ; RV64: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 5
40 ; RV64: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
[all …]
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/RISCV/
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/
H A Dselect-optimize-multiple.mir63 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
85 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
107 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
129 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
144 %8:gpr = ADDI %7, 1
188 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189 ; RV32I: DBG_VALUE [[ADDI]], $noreg
209 ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
230 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
251 ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
[all …]
/dports/emulators/jzintv/jzintv-20200712-src/examples/synth/
H A Dsynth_gfx.asm187 ADDI #20, R3
189 ADDI #20, R3
193 ADDI #8, R0
194 ADDI #8, R1
204 ADDI #20, R3
206 ADDI #8, R0
207 ADDI #20, R3
281 ADDI #32, R0
287 ADDI #KEY_Y_OFS - KEY_X_OFS, R1
321 ADDI #8, R3 ;
[all …]
/dports/lang/mit-scheme/mit-scheme-9.2/src/compiler/machines/sparc/
H A Drules3.scm300 (ADDI ,destination ,destination -4)
320 (ADDI ,from ,from -12)
328 (ADDI ,from ,from -8)
331 (ADDI ,destination ,destination -8)
337 (ADDI ,from ,from -4)
338 (ADDI ,temp2 ,temp2 -1)
339 (ADDI ,destination ,destination -4)
555 (ADDI ,dest ,regnum:second-arg 0)
610 (ADDI ,regnum:second-arg 0 ,nentries)
611 (ADDI ,regnum:third-arg ,regnum:free 0)
[all …]
/dports/math/cln/cln-1.3.6/src/base/digitseq/
H A Dcl_asm_hppa_.cc24 ADDI 16,%ret0,%ret0 // y = y+16;
28 ADDI 8,%ret0,%ret0 // y = y+8;
32 ADDI 4,%ret0,%ret0 // y = y+4;
36 ADDI 2,%ret0,%ret0 // y = y+2;
39 ADDI 1,%ret0,%ret0 // y = y+1;
/dports/lang/go-devel/go-becaeea1199b875bc24800fa88f2f4fea119bf78/src/cmd/asm/internal/asm/testdata/
H A Driscv64.s13 ADDI $2047, X5 // 9382f27f
14 ADDI $-2048, X5 // 93820280
15 ADDI $2048, X5 // 9382024093820240
16 ADDI $-2049, X5 // 938202c09382f2bf
17 ADDI $4094, X5 // 9382f27f9382f27f
18 ADDI $-4096, X5 // 9382028093820280
21 ADDI $2047, X5, X6 // 1383f27f
22 ADDI $-2048, X5, X6 // 13830280
23 ADDI $2048, X5, X6 // 1383024013030340
24 ADDI $-2049, X5, X6 // 138302c01303f3bf
[all …]
/dports/lang/clisp/clisp-df3b9f6fdcff22832898e89a989eb499c0f842ed/src/
H A Dari_asm_hppa.d66 ADDI 16,%ret0,%ret0 /* y = y+16; */
70 ADDI 8,%ret0,%ret0 /* y = y+8; */
74 ADDI 4,%ret0,%ret0 /* y = y+4; */
78 ADDI 2,%ret0,%ret0 /* y = y+2; */
81 ADDI 1,%ret0,%ret0 /* y = y+1; */

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