/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | i64_volatile_load_store.ll | 12 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 22 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 36 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 46 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 59 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 67 ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] 81 ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] 83 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 109 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 135 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 108 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 113 ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1) 114 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 145 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 151 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 157 ; CHECK: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4) 158 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 160 ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4) [all …]
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/dports/sysutils/bareos-client/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 306 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 336 exp = ADDR1 "," ADDR3; in START_TEST() 346 exp = ADDR1 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 370 #undef ADDR1 in START_TEST() 409 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 435 exp = ADDR1 "," ADDR3; in START_TEST() [all …]
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/dports/sysutils/bareos-traymonitor/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 306 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 336 exp = ADDR1 "," ADDR3; in START_TEST() 346 exp = ADDR1 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 370 #undef ADDR1 in START_TEST() 409 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 435 exp = ADDR1 "," ADDR3; in START_TEST() [all …]
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/dports/sysutils/bareos-server/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 306 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 336 exp = ADDR1 "," ADDR3; in START_TEST() 346 exp = ADDR1 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 370 #undef ADDR1 in START_TEST() 409 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 435 exp = ADDR1 "," ADDR3; in START_TEST() [all …]
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/dports/www/bareos-webui/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 306 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 336 exp = ADDR1 "," ADDR3; in START_TEST() 346 exp = ADDR1 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 370 #undef ADDR1 in START_TEST() 409 #define ADDR1 ADDR1_H ":" PORT in START_TEST() macro 435 exp = ADDR1 "," ADDR3; in START_TEST() [all …]
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/dports/net/fort/FORT-validator-1.5.3/test/rtr/db/ |
H A D | db_table_test.c | 14 #define ADDR1 htonl(0xC0000201) /* 192.0.2.1 */ macro 60 if (vrp_equals_v4(vrp, 10, ADDR1, 24, 32)) in foreach_cb() 62 if (vrp_equals_v4(vrp, 11, ADDR1, 24, 32)) in foreach_cb() 66 if (vrp_equals_v4(vrp, 10, ADDR1, 25, 32)) in foreach_cb() 68 if (vrp_equals_v4(vrp, 10, ADDR1, 24, 30)) in foreach_cb() 107 prefix4.addr.s_addr = ADDR1; in START_TEST() 125 prefix4.addr.s_addr = ADDR1; in START_TEST()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/avrlibx/third_party/eeprom_driver/ |
H A D | eeprom_driver.c | 126 NVM.ADDR1 = (addr >> 8) & 0x1F; in EEPROM_read_byte() 142 NVM.ADDR1 = (addr >> 8) & 0x1F; in EEPROM_write_byte() 163 NVM.ADDR1 = (addr >> 8) & 0x1F; in EEPROM_read_block() 186 NVM.ADDR1 = 0; in EEPROM_write_block() 201 NVM.ADDR1 = (page_addr >> 8) & 0x1F; in EEPROM_write_block() 224 NVM.ADDR1 = (addr >> 8) & 0x1F; in EEPROM_erase_page()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 10 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 12 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 18 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !5 20 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 54 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 56 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 60 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !0 62 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 10 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 12 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 18 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !5 20 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 54 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 56 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 60 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !0 62 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 10 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 12 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 18 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !5 20 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 54 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 56 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 60 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !0 62 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 10 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 12 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 18 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !5 20 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 54 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 56 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 60 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !0 62 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 10 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 12 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 18 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !5 20 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 54 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 56 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 60 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !0 62 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 10 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 12 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 18 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !5 20 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 54 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 56 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 60 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !0 62 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 10 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 12 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 18 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !5 20 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 54 ; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !0 56 ; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1 60 ; CHECK-NEXT: [[X_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !0 62 ; CHECK-NEXT: [[ADDR1I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i32 1
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 108 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0 109 ; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1) 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 114 ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1) 145 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0 146 ; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 151 ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1) 158 ; CHECK: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4) 161 ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4)
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