/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1) 114 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 151 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 152 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1) 158 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] 159 ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4) 161 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] [all …]
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/dports/sysutils/bareos-client/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 308 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 313 addrlist = dpl_addrlist_create_from_str(NULL, ADDR1 "," ADDR2 "," ADDR3); in START_TEST() 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 372 #undef ADDR2 in START_TEST() 411 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 419 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 448 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() [all …]
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/dports/sysutils/bareos-traymonitor/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 308 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 313 addrlist = dpl_addrlist_create_from_str(NULL, ADDR1 "," ADDR2 "," ADDR3); in START_TEST() 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 372 #undef ADDR2 in START_TEST() 411 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 419 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 448 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() [all …]
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/dports/sysutils/bareos-server/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 308 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 313 addrlist = dpl_addrlist_create_from_str(NULL, ADDR1 "," ADDR2 "," ADDR3); in START_TEST() 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 372 #undef ADDR2 in START_TEST() 411 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 419 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 448 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() [all …]
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/dports/www/bareos-webui/bareos-Release-20.0.3/core/src/droplet/utests/tests/ |
H A D | addrlist_utest.c | 308 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 313 addrlist = dpl_addrlist_create_from_str(NULL, ADDR1 "," ADDR2 "," ADDR3); in START_TEST() 316 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 325 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 355 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 364 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 372 #undef ADDR2 in START_TEST() 411 #define ADDR2 ADDR2_H ":" PORT in START_TEST() macro 419 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() 448 exp = ADDR1 "," ADDR2 "," ADDR3; in START_TEST() [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 11 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 13 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 19 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !5 21 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 55 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 57 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 61 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !0 63 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 11 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 13 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 19 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !5 21 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 55 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 57 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 61 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !0 63 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 11 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 13 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 19 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !5 21 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 55 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 57 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 61 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !0 63 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 11 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 13 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 19 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !5 21 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 55 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 57 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 61 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !0 63 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 11 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 13 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 19 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !5 21 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 55 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 57 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 61 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !0 63 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 11 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 13 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 19 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !5 21 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 55 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 57 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 61 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !0 63 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/LoopUnroll/ |
H A D | noalias.ll | 11 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 13 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 19 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !5 21 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 55 ; CHECK-NEXT: store i32 [[X]], i32* [[ADDR2:%.*]], align 4, !noalias !0 57 ; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1 61 ; CHECK-NEXT: store i32 [[X_2]], i32* [[ADDR2]], align 4, !noalias !0 63 ; CHECK-NEXT: [[ADDR2I_3:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i32 1
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/avrlibx/third_party/eeprom_driver/ |
H A D | eeprom_driver.c | 127 NVM.ADDR2 = 0; in EEPROM_read_byte() 143 NVM.ADDR2 = 0; in EEPROM_write_byte() 156 NVM.ADDR2 = 0; in EEPROM_read_block() 187 NVM.ADDR2 = 0; in EEPROM_write_block() 225 NVM.ADDR2 = 0; in EEPROM_erase_page()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 162 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4)
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 162 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4)
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 162 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4)
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 162 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4)
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 162 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4)
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 162 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4)
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 111 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 115 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4, align 1) 148 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 162 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4)
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/dports/deskutils/glabels/glabels-3.4.1/help/C/ |
H A D | skipfields.page | 28 following CSV file, column 5 (ADDR2) contains the second address line 34 LAST,FIRST,MI,ADDR1,ADDR2,CITY,STATE,ZIP 41 created to format these addresses. Notice that ${ADDR2} representing 50 line containing the ${ADDR2} field is completely skipped for the first
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 131 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 132 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 135 …; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4, align 1) 168 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 169 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 172 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 179 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 182 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4)
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 132 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 133 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 136 …; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4, align 1) 169 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 170 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 173 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 180 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 183 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4)
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 132 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 133 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 136 …; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4, align 1) 169 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 170 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 173 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 180 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 183 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4)
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
H A D | arm-legalize-load-store.mir | 132 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 133 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 136 …; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4, align 1) 169 ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]] 170 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 173 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 180 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]] 183 ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4)
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