| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1069/ |
| H A D | tb_ram4.vhdl | 9 constant ADDRWIDTH : natural := 12; constant
14 signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
20 signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
26 ADDRWIDTH => ADDRWIDTH,
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| H A D | tb_ram5.vhdl | 9 constant ADDRWIDTH : natural := 12; constant
14 signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
20 signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
26 ADDRWIDTH => ADDRWIDTH,
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| H A D | tb_ram41.vhdl | 9 constant ADDRWIDTH : natural := 12; constant
14 signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
20 signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
26 ADDRWIDTH => ADDRWIDTH,
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| H A D | tb_ram3.vhdl | 9 constant ADDRWIDTH : natural := 12; constant
14 signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
20 signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
26 ADDRWIDTH => ADDRWIDTH,
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| H A D | ram41.vhdl | 7 ADDRWIDTH : positive := 7; generic
14 addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
21 addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
30 type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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| H A D | ram5.vhdl | 7 ADDRWIDTH : positive := 12; generic
14 addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
21 addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
30 type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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| H A D | ram4.vhdl | 7 ADDRWIDTH : positive := 12; generic
14 addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
21 addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
30 type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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| H A D | ram3.vhdl | 7 ADDRWIDTH : positive := 12; generic
14 addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
21 addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
32 type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/synth109/ |
| H A D | ram2.vhdl | 9 ADDRWIDTH : integer := 6 generic
19 addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
20 addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
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| H A D | ram3.vhdl | 11 ADDRWIDTH : integer := 6 generic
21 addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
22 addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue467/ |
| H A D | axi_master.vhd | 32 ADDRWIDTH : positive := 12 generic
36 AWADDR : out std_logic_vector(ADDRWIDTH-1 downto 0);
50 ARADDR : out std_logic_vector(ADDRWIDTH-1 downto 0);
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| H A D | testbench2.vhdl | 46 ADDRWIDTH => AWADDR'length
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| /dports/graphics/exifprobe/exifprobe-2.0.1/ |
| H A D | defs.h | 31 #define ADDRWIDTH 8 macro
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| H A D | print.c | 272 chpr += printf("%*s: ",(ADDRWIDTH * 2) + 3,prefix); in print_tag_address()
274 chpr += printf("%*s: ",ADDRWIDTH + 1,prefix); in print_tag_address()
276 chpr += printf("%*s: ",ADDRWIDTH,prefix); in print_tag_address()
281 chpr += printf("%s%#0*lx=%-*lu: ",prefix,ADDRWIDTH+1,address,ADDRWIDTH,address); in print_tag_address()
283 chpr += printf("%s%#0*lx: ",prefix,ADDRWIDTH+1,address); in print_tag_address()
285 chpr += printf("%s%-*lu: ",prefix,ADDRWIDTH,address); in print_tag_address()
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| H A D | process.c | 2458 putindent(6 + (2 * ADDRWIDTH) + indent + 16); in process_jpeg_segments()
2475 putindent(6 + (2 * ADDRWIDTH) + indent + 16); in process_jpeg_segments()
2776 putindent(6 + (2 * ADDRWIDTH) + indent + 16); in process_jpeg_segments()
2928 putindent(6 + (2 * ADDRWIDTH) + indent + 16); in process_jpeg_segments()
3905 extraindent(indent + ADDRWIDTH); in process_app1()
4090 extraindent(indent + ADDRWIDTH); in process_app3()
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