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Searched refs:ADDR_TM_2D_TILED_THIN1 (Results 1 – 25 of 66) sorted by relevance

123

/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/libosmesa/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-libs/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp800 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
806 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
810 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1067 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1134 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1154 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1160 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1394 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1413 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1465 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp184 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2250 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2507 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3019 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3044 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3152 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp798 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
804 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
808 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1065 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1132 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1152 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1158 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1392 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1411 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1463 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp181 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1129 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1252 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1262 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1386 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2251 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2510 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3022 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3048 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3158 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-dri/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/lang/clover/mesa-21.3.6/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
H A Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/amd/addrlib/inc/
H A Daddrtypes.h176 ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles enumerator
/dports/lang/clover/mesa-21.3.6/src/amd/addrlib/inc/
H A Daddrtypes.h185 ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles enumerator
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/addrlib/inc/
H A Daddrtypes.h185 ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles enumerator

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