/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/AArch64/ |
H A D | mirnamer.mir | 35 ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr 37 ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr 49 %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32 51 %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32 53 %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32 56 %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32 57 %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32 58 %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32 59 %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32 60 %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32 [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/ |
H A D | post-ra-machine-sink.mir | 24 $w0 = ADDWrr $w1, $w19 56 $w0 = ADDWrr $w1, $w19 110 $w0 = ADDWrr $w1, $w19 115 $w0 = ADDWrr $w0, $w20 124 # CHECK: $w1 = ADDWrr $w1, $w0 148 $w0 = ADDWrr $w1, $w19 204 $w0 = ADDWrr $w0, $w19 265 $w0 = ADDWrr $w0, $w19 292 $w0 = ADDWrr $w0, $w19 318 $w0 = ADDWrr $w0, $w19 [all …]
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