| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | fcmp.mir | 79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/Mips/ |
| H A D | macro-aliases.s | 6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
|