1 //***************************************************************************** 2 // 3 // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // 6 // Redistribution and use in source and binary forms, with or without 7 // modification, are permitted provided that the following conditions 8 // are met: 9 // 10 // Redistributions of source code must retain the above copyright 11 // notice, this list of conditions and the following disclaimer. 12 // 13 // Redistributions in binary form must reproduce the above copyright 14 // notice, this list of conditions and the following disclaimer in the 15 // documentation and/or other materials provided with the 16 // distribution. 17 // 18 // Neither the name of Texas Instruments Incorporated nor the names of 19 // its contributors may be used to endorse or promote products derived 20 // from this software without specific prior written permission. 21 // 22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 // 34 //***************************************************************************** 35 36 #ifndef __HW_AES_H__ 37 #define __HW_AES_H__ 38 39 //***************************************************************************** 40 // 41 // The following are defines for the AES_P register offsets. 42 // 43 //***************************************************************************** 44 #define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third 45 // key 46 #define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit 47 // key) / CBC-MAC third key (MSW) 48 #define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC 49 // third key (LSW) 50 #define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit 51 // key) / CBC-MAC third key 52 #define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / 53 // Hash Key input 54 #define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit 55 // key) + CCM/CBC-MAC second key 56 // (MSW) / Hash Key input (MSW) 57 #define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key 58 // (LSW) / Hash Key input (LSW) 59 #define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / 60 // Hash Key input 61 #define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) 62 #define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) 63 #define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) 64 #define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) 65 #define AES_O_KEY1_2 0x00000030 // Key 66 #define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) 67 #define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) 68 #define AES_O_KEY1_1 0x0000003C // Key 69 #define AES_O_IV_IN_0 0x00000040 // Initialization Vector input 70 // (LSW) 71 #define AES_O_IV_IN_1 0x00000044 // Initialization vector input 72 #define AES_O_IV_IN_2 0x00000048 // Initialization vector input 73 #define AES_O_IV_IN_3 0x0000004C // Initialization Vector input 74 // (MSW) 75 #define AES_O_CTRL 0x00000050 // register determines the mode of 76 // operation of the AES Engine 77 #define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers 78 // (LSW and MSW) store the 79 // cryptographic data length in 80 // bytes for all modes. Once 81 // processing with this context is 82 // started@@ this length decrements 83 // to zero. Data lengths up to (2^61 84 // – 1) bytes are allowed. For GCM@@ 85 // any value up to 2^36 - 32 bytes 86 // can be used. This is because a 87 // 32-bit counter mode is used; the 88 // maximum number of 128-bit blocks 89 // is 2^32 – 2@@ resulting in a 90 // maximum number of bytes of 2^36 - 91 // 32. A write to this register 92 // triggers the engine to start 93 // using this context. This is valid 94 // for all modes except GCM and CCM. 95 // Note that for the combined 96 // modes@@ this length does not 97 // include the authentication only 98 // data; the authentication length 99 // is specified in the 100 // AES_AUTH_LENGTH register below. 101 // All modes must have a length > 0. 102 // For the combined modes@@ it is 103 // allowed to have one of the 104 // lengths equal to zero. For the 105 // basic encryption modes 106 // (ECB/CBC/CTR/ICM/CFB128) it is 107 // allowed to program zero to the 108 // length field; in that case the 109 // length is assumed infinite. All 110 // data must be byte (8-bit) 111 // aligned; bit aligned data streams 112 // are not supported by the AES 113 // Engine. For a Host read 114 // operation@@ these registers 115 // return all-zeroes. 116 #define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers 117 // (LSW and MSW) store the 118 // cryptographic data length in 119 // bytes for all modes. Once 120 // processing with this context is 121 // started@@ this length decrements 122 // to zero. Data lengths up to (2^61 123 // – 1) bytes are allowed. For GCM@@ 124 // any value up to 2^36 - 32 bytes 125 // can be used. This is because a 126 // 32-bit counter mode is used; the 127 // maximum number of 128-bit blocks 128 // is 2^32 – 2@@ resulting in a 129 // maximum number of bytes of 2^36 - 130 // 32. A write to this register 131 // triggers the engine to start 132 // using this context. This is valid 133 // for all modes except GCM and CCM. 134 // Note that for the combined 135 // modes@@ this length does not 136 // include the authentication only 137 // data; the authentication length 138 // is specified in the 139 // AES_AUTH_LENGTH register below. 140 // All modes must have a length > 0. 141 // For the combined modes@@ it is 142 // allowed to have one of the 143 // lengths equal to zero. For the 144 // basic encryption modes 145 // (ECB/CBC/CTR/ICM/CFB128) it is 146 // allowed to program zero to the 147 // length field; in that case the 148 // length is assumed infinite. All 149 // data must be byte (8-bit) 150 // aligned; bit aligned data streams 151 // are not supported by the AES 152 // Engine. For a Host read 153 // operation@@ these registers 154 // return all-zeroes. 155 #define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The 156 // authentication length register 157 // store the authentication data 158 // length in bytes for combined 159 // modes only (GCM or CCM) Supported 160 // AAD-lengths for CCM are from 0 to 161 // (2^16 - 2^8) bytes. For GCM any 162 // value up to (2^32 - 1) bytes can 163 // be used. Once processing with 164 // this context is started@@ this 165 // length decrements to zero. A 166 // write to this register triggers 167 // the engine to start using this 168 // context for GCM and CCM. For XTS 169 // this register is optionally used 170 // to load ‘j’. Loading of ‘j’ is 171 // only required if ‘j’ != 0. ‘j’ is 172 // a 28-bit value and must be 173 // written to bits [31-4] of this 174 // register. ‘j’ represents the 175 // sequential number of the 128-bit 176 // block inside the data unit. For 177 // the first block in a unit@@ this 178 // value is zero. It is not required 179 // to provide a ‘j’ for each new 180 // data block within a unit. Note 181 // that it is possible to start with 182 // a ‘j’ unequal to zero; refer to 183 // Table 4 for more details. For a 184 // Host read operation@@ these 185 // registers return all-zeroes. 186 #define AES_O_DATA_IN_0 0x00000060 // Data register to read and write 187 // plaintext/ciphertext (MSW) 188 #define AES_O_DATA_IN_1 0x00000064 // Data register to read and write 189 // plaintext/ciphertext 190 #define AES_O_DATA_IN_2 0x00000068 // Data register to read and write 191 // plaintext/ciphertext 192 #define AES_O_DATA_IN_3 0x0000006C // Data register to read and write 193 // plaintext/ciphertext (LSW) 194 #define AES_O_TAG_OUT_0 0x00000070 195 #define AES_O_TAG_OUT_1 0x00000074 196 #define AES_O_TAG_OUT_2 0x00000078 197 #define AES_O_TAG_OUT_3 0x0000007C 198 #define AES_O_REVISION 0x00000080 // Register AES_REVISION 199 #define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This 200 // register configures the DMA 201 // signals and controls the IDLE and 202 // reset logic 203 #define AES_O_SYSSTATUS 0x00000088 204 #define AES_O_IRQSTATUS 0x0000008C // This register indicates the 205 // interrupt status. If one of the 206 // interrupt bits is set the 207 // interrupt output will be asserted 208 #define AES_O_IRQENABLE 0x00000090 // This register contains an enable 209 // bit for each unique interrupt 210 // generated by the module. It 211 // matches the layout of 212 // AES_IRQSTATUS register. An 213 // interrupt is enabled when the bit 214 // in this register is set to ‘1’. 215 // An interrupt that is enabled is 216 // propagated to the SINTREQUEST_x 217 // output. All interrupts need to be 218 // enabled explicitly by writing 219 // this register. 220 221 222 223 //****************************************************************************** 224 // 225 // The following are defines for the bit fields in the AES_O_KEY2_6 register. 226 // 227 //****************************************************************************** 228 #define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data 229 #define AES_KEY2_6_KEY_S 0 230 //****************************************************************************** 231 // 232 // The following are defines for the bit fields in the AES_O_KEY2_7 register. 233 // 234 //****************************************************************************** 235 #define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data 236 #define AES_KEY2_7_KEY_S 0 237 //****************************************************************************** 238 // 239 // The following are defines for the bit fields in the AES_O_KEY2_4 register. 240 // 241 //****************************************************************************** 242 #define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data 243 #define AES_KEY2_4_KEY_S 0 244 //****************************************************************************** 245 // 246 // The following are defines for the bit fields in the AES_O_KEY2_5 register. 247 // 248 //****************************************************************************** 249 #define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data 250 #define AES_KEY2_5_KEY_S 0 251 //****************************************************************************** 252 // 253 // The following are defines for the bit fields in the AES_O_KEY2_2 register. 254 // 255 //****************************************************************************** 256 #define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data 257 #define AES_KEY2_2_KEY_S 0 258 //****************************************************************************** 259 // 260 // The following are defines for the bit fields in the AES_O_KEY2_3 register. 261 // 262 //****************************************************************************** 263 #define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data 264 #define AES_KEY2_3_KEY_S 0 265 //****************************************************************************** 266 // 267 // The following are defines for the bit fields in the AES_O_KEY2_0 register. 268 // 269 //****************************************************************************** 270 #define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data 271 #define AES_KEY2_0_KEY_S 0 272 //****************************************************************************** 273 // 274 // The following are defines for the bit fields in the AES_O_KEY2_1 register. 275 // 276 //****************************************************************************** 277 #define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data 278 #define AES_KEY2_1_KEY_S 0 279 //****************************************************************************** 280 // 281 // The following are defines for the bit fields in the AES_O_KEY1_6 register. 282 // 283 //****************************************************************************** 284 #define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data 285 #define AES_KEY1_6_KEY_S 0 286 //****************************************************************************** 287 // 288 // The following are defines for the bit fields in the AES_O_KEY1_7 register. 289 // 290 //****************************************************************************** 291 #define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data 292 #define AES_KEY1_7_KEY_S 0 293 //****************************************************************************** 294 // 295 // The following are defines for the bit fields in the AES_O_KEY1_4 register. 296 // 297 //****************************************************************************** 298 #define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data 299 #define AES_KEY1_4_KEY_S 0 300 //****************************************************************************** 301 // 302 // The following are defines for the bit fields in the AES_O_KEY1_5 register. 303 // 304 //****************************************************************************** 305 #define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data 306 #define AES_KEY1_5_KEY_S 0 307 //****************************************************************************** 308 // 309 // The following are defines for the bit fields in the AES_O_KEY1_2 register. 310 // 311 //****************************************************************************** 312 #define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data 313 #define AES_KEY1_2_KEY_S 0 314 //****************************************************************************** 315 // 316 // The following are defines for the bit fields in the AES_O_KEY1_3 register. 317 // 318 //****************************************************************************** 319 #define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data 320 #define AES_KEY1_3_KEY_S 0 321 //****************************************************************************** 322 // 323 // The following are defines for the bit fields in the AES_O_KEY1_0 register. 324 // 325 //****************************************************************************** 326 #define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data 327 #define AES_KEY1_0_KEY_S 0 328 //****************************************************************************** 329 // 330 // The following are defines for the bit fields in the AES_O_KEY1_1 register. 331 // 332 //****************************************************************************** 333 #define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data 334 #define AES_KEY1_1_KEY_S 0 335 //****************************************************************************** 336 // 337 // The following are defines for the bit fields in the AES_O_IV_IN_0 register. 338 // 339 //****************************************************************************** 340 #define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data 341 #define AES_IV_IN_0_DATA_S 0 342 //****************************************************************************** 343 // 344 // The following are defines for the bit fields in the AES_O_IV_IN_1 register. 345 // 346 //****************************************************************************** 347 #define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data 348 #define AES_IV_IN_1_DATA_S 0 349 //****************************************************************************** 350 // 351 // The following are defines for the bit fields in the AES_O_IV_IN_2 register. 352 // 353 //****************************************************************************** 354 #define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data 355 #define AES_IV_IN_2_DATA_S 0 356 //****************************************************************************** 357 // 358 // The following are defines for the bit fields in the AES_O_IV_IN_3 register. 359 // 360 //****************************************************************************** 361 #define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data 362 #define AES_IV_IN_3_DATA_S 0 363 //****************************************************************************** 364 // 365 // The following are defines for the bit fields in the AES_O_CTRL register. 366 // 367 //****************************************************************************** 368 #define AES_CTRL_CONTEXT_READY \ 369 0x80000000 // If ‘1’@@ this read-only status 370 // bit indicates that the context 371 // data registers can be overwritten 372 // and the host is permitted to 373 // write the next context. 374 375 #define AES_CTRL_SVCTXTRDY \ 376 0x40000000 // If ‘1’@@ this read-only status 377 // bit indicates that an AES 378 // authentication TAG and/or IV 379 // block(s) is/are available for the 380 // host to retrieve. This bit is 381 // only asserted if the 382 // ‘save_context’ bit is set to ‘1’. 383 // The bit is mutual exclusive with 384 // the ‘context_ready’ bit. 385 386 #define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate 387 // that an authentication TAG or 388 // result IV needs to be stored as a 389 // result context. If this bit is 390 // set@@ context output DMA and/or 391 // interrupt will be asserted if the 392 // operation is finished and related 393 // signals are enabled. 394 #define AES_CTRL_CCM_M 0x01C00000 // Defines “M” that indicated the 395 // length of the authentication 396 // field for CCM operations; the 397 // authentication field length 398 // equals two times (the value of 399 // CCM-M plus one). Note that the 400 // AES Engine always returns a 401 // 128-bit authentication field@@ of 402 // which the M least significant 403 // bytes are valid. All values are 404 // supported. 405 #define AES_CTRL_CCM_S 22 406 #define AES_CTRL_CCM_L_M 0x00380000 // Defines “L” that indicated the 407 // width of the length field for CCM 408 // operations; the length field in 409 // bytes equals the value of CMM-L 410 // plus one. Supported values for L 411 // are (programmed value): 2 (1)@@ 4 412 // (3) and 8 (7). 413 #define AES_CTRL_CCM_L_S 19 414 #define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a 415 // combined mode@@ using AES for 416 // both authentication and 417 // encryption. No additional mode 418 // selection is required. 0 Other 419 // mode selected 1 ccm mode selected 420 #define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is 421 // a combined mode@@ using the 422 // Galois field multiplier GF(2^128) 423 // for authentication and AES-CTR 424 // mode for encryption@@ the bits 425 // specify the GCM mode. 0x0 No 426 // operation 0x1 GHASH with H loaded 427 // and Y0-encrypted forced to zero 428 // 0x2 GHASH with H loaded and 429 // Y0-encrypted calculated 430 // internally 0x3 Autonomous GHASH 431 // (both H and Y0-encrypted 432 // calculated internally) 433 #define AES_CTRL_GCM_S 16 434 #define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the 435 // Direction bit must be set to ‘1’ 436 // for this mode. 0 Other mode 437 // selected 1 cbcmac mode selected 438 #define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the 439 // AES key size must be set to 440 // 128-bit for this mode. 0 Other 441 // mode selected 1 f9 selected 442 #define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the 443 // AES key size must be set to 444 // 128-bit for this mode. 0 Other 445 // mode selected 1 f8 selected 446 #define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; 447 // the bits specify the XTS mode.01 448 // = Previous/intermediate tweak 449 // value and ‘j’ loaded (value is 450 // loaded via IV@@ j is loaded via 451 // the AAD length register) 0x0 No 452 // operation 0x1 453 // Previous/intermediate tweak value 454 // and ‘j’ loaded (value is loaded 455 // via IV@@ j is loaded via the AAD 456 // length register) 0x2 Key2@@ i and 457 // j loaded (i is loaded via IV@@ j 458 // is loaded via the AAD length 459 // register) 0x3 Key2 and i loaded@@ 460 // j=0 (i is loaded via IV) 461 #define AES_CTRL_XTS_S 11 462 #define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback 463 // mode (CFB128) is selected. 0 464 // other mode selected 1 cfb 465 // selected 466 #define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) 467 // is selected@@ this is a counter 468 // mode with a 16-bit wide counter. 469 // 0 Other mode selected. 1 ICM mode 470 // selected 471 #define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for 472 // AES-CTR mode 0x0 Counter is 32 473 // bits 0x1 Counter is 64 bits 0x2 474 // Counter is 128 bits 0x3 Counter 475 // is 192 bits 476 #define AES_CTRL_CTR_WIDTH_S 7 477 #define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for 478 // GCM and CCM@@ when 479 // encryption/decryption is 480 // required. 0 Other mode selected 1 481 // Counter mode 482 #define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc 483 // mode 484 #define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is 485 // 128 bits. 0x2 Key is 192 bits 0x3 486 // Key is 256 487 #define AES_CTRL_KEY_SIZE_S 3 488 #define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt 489 // operation is performed. If set to 490 // ‘0’ a decrypt operation is 491 // performed. Read 0 decryption is 492 // selected Read 1 Encryption is 493 // selected 494 #define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status 495 // bit indicates that the 16-byte 496 // input buffer is empty@@ and the 497 // host is permitted to write the 498 // next block of data. 499 #define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status 500 // bit indicates that an AES output 501 // block is available for the host 502 // to retrieve. 503 //****************************************************************************** 504 // 505 // The following are defines for the bit fields in the 506 // AES_O_C_LENGTH_0 register. 507 // 508 //****************************************************************************** 509 //****************************************************************************** 510 // 511 // The following are defines for the bit fields in the 512 // AES_O_C_LENGTH_1 register. 513 // 514 //****************************************************************************** 515 #define AES_C_LENGTH_1_LENGTH_M \ 516 0x1FFFFFFF // Data length (MSW) length 517 // registers (LSW and MSW) store the 518 // cryptographic data length in 519 // bytes for all modes. Once 520 // processing with this context is 521 // started@@ this length decrements 522 // to zero. Data lengths up to (2^61 523 // – 1) bytes are allowed. For GCM@@ 524 // any value up to 2^36 - 32 bytes 525 // can be used. This is because a 526 // 32-bit counter mode is used; the 527 // maximum number of 128-bit blocks 528 // is 2^32 – 2@@ resulting in a 529 // maximum number of bytes of 2^36 - 530 // 32. A write to this register 531 // triggers the engine to start 532 // using this context. This is valid 533 // for all modes except GCM and CCM. 534 // Note that for the combined 535 // modes@@ this length does not 536 // include the authentication only 537 // data; the authentication length 538 // is specified in the 539 // AES_AUTH_LENGTH register below. 540 // All modes must have a length > 0. 541 // For the combined modes@@ it is 542 // allowed to have one of the 543 // lengths equal to zero. For the 544 // basic encryption modes 545 // (ECB/CBC/CTR/ICM/CFB128) it is 546 // allowed to program zero to the 547 // length field; in that case the 548 // length is assumed infinite. All 549 // data must be byte (8-bit) 550 // aligned; bit aligned data streams 551 // are not supported by the AES 552 // Engine. For a Host read 553 // operation@@ these registers 554 // return all-zeroes. 555 556 #define AES_C_LENGTH_1_LENGTH_S 0 557 //****************************************************************************** 558 // 559 // The following are defines for the bit fields in the 560 // AES_O_AUTH_LENGTH register. 561 // 562 //****************************************************************************** 563 #define AES_AUTH_LENGTH_AUTH_M \ 564 0xFFFFFFFF // data 565 566 #define AES_AUTH_LENGTH_AUTH_S 0 567 //****************************************************************************** 568 // 569 // The following are defines for the bit fields in the AES_O_DATA_IN_0 register. 570 // 571 //****************************************************************************** 572 #define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 573 #define AES_DATA_IN_0_DATA_S 0 574 //****************************************************************************** 575 // 576 // The following are defines for the bit fields in the AES_O_DATA_IN_1 register. 577 // 578 //****************************************************************************** 579 #define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 580 #define AES_DATA_IN_1_DATA_S 0 581 //****************************************************************************** 582 // 583 // The following are defines for the bit fields in the AES_O_DATA_IN_2 register. 584 // 585 //****************************************************************************** 586 #define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 587 #define AES_DATA_IN_2_DATA_S 0 588 //****************************************************************************** 589 // 590 // The following are defines for the bit fields in the AES_O_DATA_IN_3 register. 591 // 592 //****************************************************************************** 593 #define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 594 #define AES_DATA_IN_3_DATA_S 0 595 //****************************************************************************** 596 // 597 // The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. 598 // 599 //****************************************************************************** 600 #define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) 601 #define AES_TAG_OUT_0_HASH_S 0 602 //****************************************************************************** 603 // 604 // The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. 605 // 606 //****************************************************************************** 607 #define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) 608 #define AES_TAG_OUT_1_HASH_S 0 609 //****************************************************************************** 610 // 611 // The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. 612 // 613 //****************************************************************************** 614 #define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) 615 #define AES_TAG_OUT_2_HASH_S 0 616 //****************************************************************************** 617 // 618 // The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. 619 // 620 //****************************************************************************** 621 #define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) 622 #define AES_TAG_OUT_3_HASH_S 0 623 //****************************************************************************** 624 // 625 // The following are defines for the bit fields in the AES_O_REVISION register. 626 // 627 //****************************************************************************** 628 #define AES_REVISION_SCHEME_M 0xC0000000 629 #define AES_REVISION_SCHEME_S 30 630 #define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software 631 // compatible module family. If 632 // there is no level of software 633 // compatibility a new Func number 634 // (and hence REVISION) should be 635 // assigned. 636 #define AES_REVISION_FUNC_S 16 637 #define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by 638 // IP design owner. RTL follows a 639 // numbering such as X.Y.R.Z which 640 // are explained in this table. R 641 // changes ONLY when: (1) PDS 642 // uploads occur which may have been 643 // due to spec changes (2) Bug fixes 644 // occur (3) Resets to '0' when X or 645 // Y changes. Design team has an 646 // internal 'Z' (customer invisible) 647 // number which increments on every 648 // drop that happens due to DV and 649 // RTL updates. Z resets to 0 when R 650 // increments. 651 #define AES_REVISION_R_RTL_S 11 652 #define AES_REVISION_X_MAJOR_M \ 653 0x00000700 // Major Revision (X)@@ maintained 654 // by IP specification owner. X 655 // changes ONLY when: (1) There is a 656 // major feature addition. An 657 // example would be adding Master 658 // Mode to Utopia Level2. The Func 659 // field (or Class/Type in old PID 660 // format) will remain the same. X 661 // does NOT change due to: (1) Bug 662 // fixes (2) Change in feature 663 // parameters. 664 665 #define AES_REVISION_X_MAJOR_S 8 666 #define AES_REVISION_CUSTOM_M 0x000000C0 667 #define AES_REVISION_CUSTOM_S 6 668 #define AES_REVISION_Y_MINOR_M \ 669 0x0000003F // Minor Revision (Y)@@ maintained 670 // by IP specification owner. Y 671 // changes ONLY when: (1) Features 672 // are scaled (up or down). 673 // Flexibility exists in that this 674 // feature scalability may either be 675 // represented in the Y change or a 676 // specific register in the IP that 677 // indicates which features are 678 // exactly available. (2) When 679 // feature creeps from Is-Not list 680 // to Is list. But this may not be 681 // the case once it sees silicon; in 682 // which case X will change. Y does 683 // NOT change due to: (1) Bug fixes 684 // (2) Typos or clarifications (3) 685 // major functional/feature 686 // change/addition/deletion. Instead 687 // these changes may be reflected 688 // via R@@ S@@ X as applicable. Spec 689 // owner maintains a 690 // customer-invisible number 'S' 691 // which changes due to: (1) 692 // Typos/clarifications (2) Bug 693 // documentation. Note that this bug 694 // is not due to a spec change but 695 // due to implementation. 696 // Nevertheless@@ the spec tracks 697 // the IP bugs. An RTL release (say 698 // for silicon PG1.1) that occurs 699 // due to bug fix should document 700 // the corresponding spec number 701 // (X.Y.S) in its release notes. 702 703 #define AES_REVISION_Y_MINOR_S 0 704 //****************************************************************************** 705 // 706 // The following are defines for the bit fields in the AES_O_SYSCONFIG register. 707 // 708 //****************************************************************************** 709 #define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ 710 0x00000200 // If set to '1' the two context 711 // out requests 712 // (dma_req_context_out_en@@ Bit [8] 713 // above@@ and context_out interrupt 714 // enable@@ Bit [3] of AES_IRQENABLE 715 // register) are mapped on the 716 // corresponding data output request 717 // bit. In this case@@ the original 718 // ‘context out’ bit values are 719 // ignored. 720 721 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ 722 0x00000100 // If set to ‘1’@@ the DMA context 723 // output request is enabled (for 724 // context data out@@ e.g. TAG for 725 // authentication modes). 0 Dma 726 // disabled 1 Dma enabled 727 728 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ 729 0x00000080 // If set to ‘1’@@ the DMA context 730 // request is enabled. 0 Dma 731 // disabled 1 Dma enabled 732 733 #define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ 734 0x00000040 // If set to ‘1’@@ the DMA output 735 // request is enabled. 0 Dma 736 // disabled 1 Dma enabled 737 738 #define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ 739 0x00000020 // If set to ‘1’@@ the DMA input 740 // request is enabled. 0 Dma 741 // disabled 1 Dma enabled 742 743 //****************************************************************************** 744 // 745 // The following are defines for the bit fields in the AES_O_SYSSTATUS register. 746 // 747 //****************************************************************************** 748 #define AES_SYSSTATUS_RESETDONE \ 749 0x00000001 750 751 //****************************************************************************** 752 // 753 // The following are defines for the bit fields in the AES_O_IRQSTATUS register. 754 // 755 //****************************************************************************** 756 #define AES_IRQSTATUS_CONTEXT_OUT \ 757 0x00000008 // This bit indicates 758 // authentication tag (and IV) 759 // interrupt(s) is/are active and 760 // triggers the interrupt output. 761 762 #define AES_IRQSTATUS_DATA_OUT \ 763 0x00000004 // This bit indicates data output 764 // interrupt is active and triggers 765 // the interrupt output. 766 767 #define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input 768 // interrupt is active and triggers 769 // the interrupt output. 770 #define AES_IRQSTATUS_CONTEX_IN \ 771 0x00000001 // This bit indicates context 772 // interrupt is active and triggers 773 // the interrupt output. 774 775 //****************************************************************************** 776 // 777 // The following are defines for the bit fields in the AES_O_IRQENABLE register. 778 // 779 //****************************************************************************** 780 #define AES_IRQENABLE_CONTEXT_OUT \ 781 0x00000008 // This bit indicates 782 // authentication tag (and IV) 783 // interrupt(s) is/are active and 784 // triggers the interrupt output. 785 786 #define AES_IRQENABLE_DATA_OUT \ 787 0x00000004 // This bit indicates data output 788 // interrupt is active and triggers 789 // the interrupt output. 790 791 #define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input 792 // interrupt is active and triggers 793 // the interrupt output. 794 #define AES_IRQENABLE_CONTEX_IN \ 795 0x00000001 // This bit indicates context 796 // interrupt is active and triggers 797 // the interrupt output. 798 799 800 801 802 #endif // __HW_AES_H__ 803