/dports/graphics/libosmesa/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/lang/clover/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/mesa-libs/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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/dports/graphics/mesa-dri/mesa-21.3.6/src/mesa/drivers/dri/radeon/ |
H A D | radeon_state_init.c | 520 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() macro 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) in radeonInitState() 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); in radeonInitState() 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); in radeonInitState() 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); in radeonInitState() 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); in radeonInitState() 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); in radeonInitState() 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); in radeonInitState() 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState() 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState() [all …]
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