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Searched refs:AN0 (Results 1 – 25 of 908) sorted by relevance

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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dm10200-opc.c43 #define AN0 (DM1+1) macro
47 #define AN1 (AN0+1)
164 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
201 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
202 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
239 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
245 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
249 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
252 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
267 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
H A Dm10300-opc.c54 #define AN0 (DM2+1) macro
58 #define AN1 (AN0+1)
448 { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
451 { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
452 { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
464 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
764 { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
766 { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
790 { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
831 { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
H A Dm10300-opc.c56 #define AN0 (DM2+1) macro
60 #define AN1 (AN0+1)
450 { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
453 { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
454 { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
466 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
766 { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
768 { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
792 { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
833 { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
H A Dm10300-opc.c56 #define AN0 (DM2+1) macro
60 #define AN1 (AN0+1)
450 { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
453 { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
454 { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
466 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
766 { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
768 { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
792 { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
833 { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dm10200-opc.c43 #define AN0 (DM1+1) macro
47 #define AN1 (AN0+1)
164 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
201 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
202 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
239 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
245 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
249 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
252 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
267 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
H A Dm10300-opc.c53 #define AN0 (DM2+1) macro
57 #define AN1 (AN0+1)
447 { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
450 { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
451 { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
463 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
763 { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
765 { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
789 { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
830 { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
H A Dm10300-opc.c56 #define AN0 (DM2+1) macro
60 #define AN1 (AN0+1)
450 { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
453 { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
454 { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
466 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
766 { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
768 { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
792 { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
833 { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
H A Dm10300-opc.c57 #define AN0 (DM2+1) macro
61 #define AN1 (AN0+1)
451 { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
454 { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
455 { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
467 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
767 { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
769 { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
793 { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
834 { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
[all …]
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
/dports/devel/gdb/gdb-11.1/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dm10200-opc.c43 #define AN0 (DM1+1) macro
47 #define AN1 (AN0+1)
164 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
201 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
202 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
239 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
245 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
249 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
252 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
267 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dm10200-opc.c43 #define AN0 (DM1+1) macro
47 #define AN1 (AN0+1)
164 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
201 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
202 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
239 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
245 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
249 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
252 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
267 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
/dports/devel/binutils/binutils-2.37/opcodes/
H A Dm10200-opc.c46 #define AN0 (DM1+1) macro
50 #define AN1 (AN0+1)
167 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
204 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
242 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
248 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
252 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
255 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
270 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
[all …]
/dports/misc/gpsim/gpsim-0.31.0/src/
H A Dp16f87x.cc423 comparator.cmcon.set_configuration(1, 0, AN0, AN3, AN0, AN3, ZERO); in create_sfr_map()
425 comparator.cmcon.set_configuration(1, 1, AN0, AN3, AN0, AN3, OUT0); in create_sfr_map()
427 comparator.cmcon.set_configuration(1, 2, AN0, AN3, AN0, AN3, NO_OUT); in create_sfr_map()
429 comparator.cmcon.set_configuration(1, 3, AN0, AN3, AN0, AN3, OUT0); in create_sfr_map()
431 comparator.cmcon.set_configuration(1, 4, AN0, AN3, AN0, AN3, NO_OUT); in create_sfr_map()
433 comparator.cmcon.set_configuration(1, 5, AN0, AN3, AN0, AN3, OUT0); in create_sfr_map()
871 comparator.cmcon.set_configuration(1, 0, AN0, AN3, AN0, AN3, ZERO); in create_sfr_map()
873 comparator.cmcon.set_configuration(1, 1, AN0, AN3, AN0, AN3, OUT0); in create_sfr_map()
875 comparator.cmcon.set_configuration(1, 2, AN0, AN3, AN0, AN3, NO_OUT); in create_sfr_map()
877 comparator.cmcon.set_configuration(1, 3, AN0, AN3, AN0, AN3, OUT0); in create_sfr_map()
[all …]
H A Dp16f62x.cc129 comparator.cmcon.set_configuration(1, 0, AN0, AN3, AN0, AN3, ZERO); in create_sfr_map()
131 comparator.cmcon.set_configuration(1, 1, AN0, AN2, AN3, AN2, NO_OUT); in create_sfr_map()
133 comparator.cmcon.set_configuration(1, 2, AN0, VREF, AN3, VREF, NO_OUT); in create_sfr_map()
135 comparator.cmcon.set_configuration(1, 3, AN0, AN2, AN0, AN2, NO_OUT); in create_sfr_map()
137 comparator.cmcon.set_configuration(1, 4, AN0, AN3, AN0, AN3, NO_OUT); in create_sfr_map()
141 comparator.cmcon.set_configuration(1, 6, AN0, AN2, AN0, AN2, OUT0); in create_sfr_map()
/dports/lang/sdcc/sdcc-4.0.0/support/scripts/
H A Dpic14-header-parser.pl2494 ADC=AN0:RA0,AN1:RA1,AN2:RA2
2499 ADC=AN0:GP0,AN1:GP1,AN2:GP2,AN3:GP4
2505 ADC=AN0:GP0,AN1:GP1,AN2:GP2,AN3:GP4
2509 ADC=AN0:RA0,AN1:RA1,AN2:RA2,AN3:RA4
2515 ADC=AN0:RA0,AN1:RA1,AN2:RA2,AN3:RA4
2520 ADC=AN0:RA0,AN1:RA1,AN2:RA2,AN3:RA4
2525 ADC=AN0:RA0,AN1:RA1,AN2:RA2,AN3:RA4
2532 ADC=AN0:RA0,AN1:RA1,AN2:RA2,AN3:RA4
2538 ADC=AN0:RA0,AN1:RA1,AN2:RA2,AN3:RA4
2570 ADC=AN0:RA0,AN1:RA1,AN2:RA2,AN3:RA3
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/sim/mn10300/
H A Dmn10300.igen43 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
77 State.regs[REG_A0+AN0] = IMM8;
82 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
95 4.0x3,11,2.AN0:S0b:::mov
366 4.0x5,11,2.AN0+8.D8:S1a:::mov
374 State.regs[REG_A0 + AN0]
388 State.regs[REG_A0 + AN0]
402 State.regs[REG_A0 + AN0]
445 State.regs[REG_A0 + AN0]
465 4.0x6,2.DM1,2.AN0:S0d:::mov
[all …]
/dports/devel/gdb761/gdb-7.6.1/sim/mn10300/
H A Dmn10300.igen43 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
77 State.regs[REG_A0+AN0] = IMM8;
82 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
95 4.0x3,11,2.AN0:S0b:::mov
366 4.0x5,11,2.AN0+8.D8:S1a:::mov
374 State.regs[REG_A0 + AN0]
388 State.regs[REG_A0 + AN0]
402 State.regs[REG_A0 + AN0]
445 State.regs[REG_A0 + AN0]
465 4.0x6,2.DM1,2.AN0:S0d:::mov
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Dmn10300.igen43 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
77 State.regs[REG_A0+AN0] = IMM8;
82 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
95 4.0x3,11,2.AN0:S0b:::mov
366 4.0x5,11,2.AN0+8.D8:S1a:::mov
374 State.regs[REG_A0 + AN0]
388 State.regs[REG_A0 + AN0]
402 State.regs[REG_A0 + AN0]
445 State.regs[REG_A0 + AN0]
465 4.0x6,2.DM1,2.AN0:S0d:::mov
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Dmn10300.igen43 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
77 State.regs[REG_A0+AN0] = IMM8;
82 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
95 4.0x3,11,2.AN0:S0b:::mov
366 4.0x5,11,2.AN0+8.D8:S1a:::mov
374 State.regs[REG_A0 + AN0]
388 State.regs[REG_A0 + AN0]
402 State.regs[REG_A0 + AN0]
445 State.regs[REG_A0 + AN0]
465 4.0x6,2.DM1,2.AN0:S0d:::mov
[all …]

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