| /dports/devel/avr-gdb/gdb-7.3.1/sim/arm/ |
| H A D | armemu.c | 4701 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4717 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4781 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4797 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4905 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4923 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4998 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
5013 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
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| H A D | armdefs.h | 384 #define ARMul_CP15_R5_ST_ALIGN 0x0001 macro
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| H A D | ChangeLog | 462 ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
|
| /dports/devel/gdb761/gdb-7.6.1/sim/arm/ |
| H A D | armemu.c | 4700 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4716 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4780 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4796 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4904 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4922 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4997 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
5012 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
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| H A D | armdefs.h | 383 #define ARMul_CP15_R5_ST_ALIGN 0x0001 macro
|
| H A D | ChangeLog | 529 ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/arm/ |
| H A D | armemu.c | 4406 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4422 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4486 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4502 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4610 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4628 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4703 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
4718 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
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| H A D | armdefs.h | 371 #define ARMul_CP15_R5_ST_ALIGN 0x0001 macro
|
| H A D | ChangeLog | 285 ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/arm/ |
| H A D | armemu.c | 4406 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4422 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadMult()
4486 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4502 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in LoadSMult()
4610 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4628 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreMult()
4703 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
4718 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); in StoreSMult()
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| H A D | armdefs.h | 371 #define ARMul_CP15_R5_ST_ALIGN 0x0001 macro
|
| H A D | ChangeLog | 285 ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
|