| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in EmitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in EmitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in EmitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx; in EmitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| H A D | MipsMCNaCl.h | 19 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 125 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
131 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
158 unsigned AddrIdx; in EmitInstruction() local
160 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction()
165 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction()
171 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction()
211 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
232 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
243 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
251 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 125 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
131 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
158 unsigned AddrIdx; in EmitInstruction() local
160 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction()
165 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction()
171 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction()
211 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
232 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
243 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
251 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
| /dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/IGC/VectorCompiler/lib/GenXCodeGen/ |
| H A D | GenXLowering.cpp | 743 AddrIdx = 3; in splitGatherScatter()
750 AddrIdx = 2; in splitGatherScatter()
758 AddrIdx = 4; in splitGatherScatter()
775 AddrIdx = 5; in splitGatherScatter()
779 AddrIdx = 4; in splitGatherScatter()
784 AddrIdx = 4; in splitGatherScatter()
791 AddrIdx = 4; in splitGatherScatter()
797 AddrIdx = 5; in splitGatherScatter()
800 AddrIdx = 4; in splitGatherScatter()
804 AddrIdx = 4; in splitGatherScatter()
[all …]
|
| /dports/devel/py-keystone-engine/keystone-engine-0.9.1-3/src/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|