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/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_sim.v3646 wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; net
3648 wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated);
3662 else assign A_MULT = Ar12_gated;