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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
H A Dinlineasm-constraint-R.ll11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
53 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
54 ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Mips/
H A Dinlineasm_constraint_ZC.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/
H A Dinlineasm-constraint-ZC-1.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Mips/
H A Dinlineasm_constraint_ZC.ll13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
29 ; ALL: lw $1, -4($[[BASEPTR]])
43 ; ALL: lw $1, 4($[[BASEPTR]])
57 ; ALL: lw $1, 252($[[BASEPTR]])
76 ; 12BIT: lw $1, 256($[[BASEPTR]])
77 ; 16BIT: lw $1, 256($[[BASEPTR]])
97 ; 12BIT: lw $1, 2044($[[BASEPTR]])
98 ; 16BIT: lw $1, 2044($[[BASEPTR]])
120 ; 16BIT: lw $1, 2048($[[BASEPTR]])
[all …]

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