/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsPcu.h | 77 #define B_PCH_LPC_COMMAND_SERR_EN BIT8 // SERR# Enable 94 #define B_PCH_LPC_DEV_STS_MDPED BIT8 // Data Parity Error 202 #define B_PCH_LPC_FWH_BIOS_DEC_EC0 BIT8 // C0-C8 Enable 315 #define B_PCH_ILB_BIOS_CNTL_PFE BIT8 // Prefetch Enable 395 #define B_PCH_ILB_OIC_AEN BIT8 // APIC Enable 449 #define B_PCH_ILB_LPCC_LPCCLK_SLC BIT8 // iLPCCLK Mux Select 711 #define B_PCH_PMC_GEN_PMCON_RTC_RESERVED BIT8 // RTC Reserved 799 #define B_PCH_PMC_GPI_ROUT_4 (BIT9 | BIT8) 862 #define B_PCH_PMC_PSS_PG_STS_USH_CTL BIT8 // USH Control 892 #define B_PCH_PMC_D3_STS_0_SCCF0 BIT8 // SCC Function 0 [all …]
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H A D | PchRegsLpss.h | 66 #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable 120 #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable 151 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable 205 #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable 238 #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable 292 #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable 325 #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable 379 #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable 417 #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable 471 #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
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H A D | PchRegsSata.h | 69 #define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable 86 #define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected 161 #define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable 170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /… 177 #define B_PCH_SATA_PORT0_DISABLED BIT8 193 #define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsPcu.h | 71 #define B_PCH_LPC_COMMAND_SERR_EN BIT8 // SERR# Enable 88 #define B_PCH_LPC_DEV_STS_MDPED BIT8 // Data Parity Error 196 #define B_PCH_LPC_FWH_BIOS_DEC_EC0 BIT8 // C0-C8 Enable 309 #define B_PCH_ILB_BIOS_CNTL_PFE BIT8 // Prefetch Enable 389 #define B_PCH_ILB_OIC_AEN BIT8 // APIC Enable 443 #define B_PCH_ILB_LPCC_LPCCLK_SLC BIT8 // iLPCCLK Mux Select 705 #define B_PCH_PMC_GEN_PMCON_RTC_RESERVED BIT8 // RTC Reserved 793 #define B_PCH_PMC_GPI_ROUT_4 (BIT9 | BIT8) 856 #define B_PCH_PMC_PSS_PG_STS_USH_CTL BIT8 // USH Control 886 #define B_PCH_PMC_D3_STS_0_SCCF0 BIT8 // SCC Function 0 [all …]
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H A D | PchRegsLpss.h | 60 #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable 114 #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable 145 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable 199 #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable 232 #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable 286 #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable 319 #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable 373 #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable 411 #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable 465 #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
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H A D | PchRegsSata.h | 63 #define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable 80 #define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected 155 #define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable 164 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /… 171 #define B_PCH_SATA_PORT0_DISABLED BIT8 187 #define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/ |
H A D | PmcRegs.h | 47 #define B_ACPI_IO_PM1_STS_PWRBTN BIT8 56 #define B_ACPI_IO_PM1_EN_PWRBTN BIT8 128 #define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8 140 #define B_ACPI_IO_GPE0_STS_127_96_RI BIT8 154 #define B_ACPI_IO_GPE0_EN_127_96_RI BIT8 167 #define B_TCO_IO_TCO1_STS_BIOSWR BIT8 205 #define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8 242 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsPmc.h | 42 #define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 ///< PWRM… 133 #define B_PCH_ACPI_PM1_STS_PWRBTN BIT8 150 #define B_PCH_ACPI_PM1_EN_PWRBTN BIT8 228 #define B_PCH_SMI_STS_PM1_STS_REG BIT8 266 #define B_PCH_DEVACT_STS_PIRQCG BIT8 306 #define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8 333 #define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8 359 #define B_PCH_TCO1_STS_BIOSWR BIT8 386 #define B_PCH_TCO_CNT_NMI_NOW BIT8 505 #define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8) [all …]
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
H A D | PchRegsPmc.h | 43 #define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 ///< PWRM… 134 #define B_PCH_ACPI_PM1_STS_PWRBTN BIT8 151 #define B_PCH_ACPI_PM1_EN_PWRBTN BIT8 229 #define B_PCH_SMI_STS_PM1_STS_REG BIT8 267 #define B_PCH_DEVACT_STS_PIRQCG BIT8 307 #define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8 334 #define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8 360 #define B_PCH_TCO1_STS_BIOSWR BIT8 387 #define B_PCH_TCO_CNT_NMI_NOW BIT8 506 #define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8) [all …]
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsPmc.h | 59 #define B_ACPI_IO_PM1_STS_PWRBTN BIT8 75 #define B_ACPI_IO_PM1_EN_PWRBTN BIT8 152 #define B_ACPI_IO_SMI_STS_PM1_STS_REG BIT8 190 #define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8 232 #define B_ACPI_IO_GPE0_STS_127_96_RI BIT8 260 #define B_ACPI_IO_GPE0_EN_127_96_RI BIT8 286 #define B_TCO_IO_TCO1_STS_BIOSWR BIT8 381 #define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8 443 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C0 BIT8 557 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8) [all …]
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/tlcs90/ |
H A D | tlcs90d.cpp | 152 #define BIT8( N,I ) m_mode##N = e_mode::BIT8; m_r##N = I; macro 444 … OP( BIT,6 ) BIT8( 1, b1 - 0xa8 ) MR16( 2, b0 - 0xe0 ) return; // BIT b,(gg) in decode() 446 … OP( RES,10 ) BIT8( 1, b1 - 0xb0 ) MR16( 2, b0 - 0xe0 ) return; // RES b,(gg) in decode() 448 … OP( SET,10 ) BIT8( 1, b1 - 0xb8 ) MR16( 2, b0 - 0xe0 ) return; // SET b,(gg) in decode() 516 … OP( BIT,10 ) BIT8( 1, b3 - 0xa8 ) MI16( 2, imm16 ) return; // BIT b,(mn) in decode() 518 … OP( RES,14 ) BIT8( 1, b3 - 0xb0 ) MI16( 2, imm16 ) return; // RES b,(mn) in decode() 520 … OP( SET,14 ) BIT8( 1, b3 - 0xb8 ) MI16( 2, imm16 ) return; // SET b,(mn) in decode() 922 OP( TSET,8 ) BIT8( 1, b1 - 0x18 ) R8( 2, b0 - 0xf8 ) return; // TSET b,g in decode() 924 OP( BIT,4 ) BIT8( 1, b1 - 0xa8 ) R8( 2, b0 - 0xf8 ) return; // BIT b,g in decode() 926 OP( RES,4 ) BIT8( 1, b1 - 0xb0 ) R8( 2, b0 - 0xf8 ) return; // RES b,g in decode() [all …]
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/tlcs90/ |
H A D | tlcs90d.cpp | 152 #define BIT8( N,I ) m_mode##N = e_mode::BIT8; m_r##N = I; macro 444 … OP( BIT,6 ) BIT8( 1, b1 - 0xa8 ) MR16( 2, b0 - 0xe0 ) return; // BIT b,(gg) in decode() 446 … OP( RES,10 ) BIT8( 1, b1 - 0xb0 ) MR16( 2, b0 - 0xe0 ) return; // RES b,(gg) in decode() 448 … OP( SET,10 ) BIT8( 1, b1 - 0xb8 ) MR16( 2, b0 - 0xe0 ) return; // SET b,(gg) in decode() 516 … OP( BIT,10 ) BIT8( 1, b3 - 0xa8 ) MI16( 2, imm16 ) return; // BIT b,(mn) in decode() 518 … OP( RES,14 ) BIT8( 1, b3 - 0xb0 ) MI16( 2, imm16 ) return; // RES b,(mn) in decode() 520 … OP( SET,14 ) BIT8( 1, b3 - 0xb8 ) MI16( 2, imm16 ) return; // SET b,(mn) in decode() 922 OP( TSET,8 ) BIT8( 1, b1 - 0x18 ) R8( 2, b0 - 0xf8 ) return; // TSET b,g in decode() 924 OP( BIT,4 ) BIT8( 1, b1 - 0xa8 ) R8( 2, b0 - 0xf8 ) return; // BIT b,g in decode() 926 OP( RES,4 ) BIT8( 1, b1 - 0xb0 ) R8( 2, b0 - 0xf8 ) return; // RES b,g in decode() [all …]
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 82 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Exce… 96 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 108 #define INSTS_TSFF BIT8 // Tx Status FIFO full 142 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 149 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 175 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du… 203 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 252 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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/dports/chinese/gcin/gcin-2.9.0/IMdkit/lib/ |
H A D | i18nIMProto.c | 95 _FRAME(BIT8), /* number of byte */ 179 _FRAME(BIT8), /* major-opcode */ 180 _FRAME(BIT8), /* minor-opcode */ 200 _FRAME(BIT8), /* byte order */ 221 _FRAME(BIT8), /* auth-data1 */ 230 _FRAME(BIT8), 238 _FRAME(BIT8), /* auth-data1 */ 515 _FRAME(BIT8), /* type */ 516 _FRAME(BIT8), /* detail */ 527 _FRAME(BIT8), /* sameScreen */ [all …]
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/dports/chinese/gcin-qt5/gcin-2.9.0/IMdkit/lib/ |
H A D | i18nIMProto.c | 95 _FRAME(BIT8), /* number of byte */ 179 _FRAME(BIT8), /* major-opcode */ 180 _FRAME(BIT8), /* minor-opcode */ 200 _FRAME(BIT8), /* byte order */ 221 _FRAME(BIT8), /* auth-data1 */ 230 _FRAME(BIT8), 238 _FRAME(BIT8), /* auth-data1 */ 515 _FRAME(BIT8), /* type */ 516 _FRAME(BIT8), /* detail */ 527 _FRAME(BIT8), /* sameScreen */ [all …]
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/dports/net-im/telegram-desktop/tdesktop-3.2.5-full/Telegram/ThirdParty/nimf/modules/services/xim/IMdkit/ |
H A D | i18nIMProto.c | 95 _FRAME(BIT8), /* number of byte */ 179 _FRAME(BIT8), /* major-opcode */ 180 _FRAME(BIT8), /* minor-opcode */ 200 _FRAME(BIT8), /* byte order */ 221 _FRAME(BIT8), /* auth-data1 */ 230 _FRAME(BIT8), 238 _FRAME(BIT8), /* auth-data1 */ 515 _FRAME(BIT8), /* type */ 516 _FRAME(BIT8), /* detail */ 527 _FRAME(BIT8), /* sameScreen */ [all …]
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/dports/chinese/gcin-gtk3/gcin-2.9.0/IMdkit/lib/ |
H A D | i18nIMProto.c | 95 _FRAME(BIT8), /* number of byte */ 179 _FRAME(BIT8), /* major-opcode */ 180 _FRAME(BIT8), /* minor-opcode */ 200 _FRAME(BIT8), /* byte order */ 221 _FRAME(BIT8), /* auth-data1 */ 230 _FRAME(BIT8), 238 _FRAME(BIT8), /* auth-data1 */ 515 _FRAME(BIT8), /* type */ 516 _FRAME(BIT8), /* detail */ 527 _FRAME(BIT8), /* sameScreen */ [all …]
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/dports/net-im/telegram-desktop/tdesktop-3.2.5-full/Telegram/ThirdParty/hime/src/IMdkit/lib/ |
H A D | i18nIMProto.c | 95 _FRAME(BIT8), /* number of byte */ 179 _FRAME(BIT8), /* major-opcode */ 180 _FRAME(BIT8), /* minor-opcode */ 200 _FRAME(BIT8), /* byte order */ 221 _FRAME(BIT8), /* auth-data1 */ 230 _FRAME(BIT8), 238 _FRAME(BIT8), /* auth-data1 */ 515 _FRAME(BIT8), /* type */ 516 _FRAME(BIT8), /* detail */ 527 _FRAME(BIT8), /* sameScreen */ [all …]
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/dports/textproc/ibus/ibus-1.5.24/util/IMdkit/ |
H A D | i18nIMProto.c | 95 _FRAME(BIT8), /* number of byte */ 179 _FRAME(BIT8), /* major-opcode */ 180 _FRAME(BIT8), /* minor-opcode */ 200 _FRAME(BIT8), /* byte order */ 221 _FRAME(BIT8), /* auth-data1 */ 230 _FRAME(BIT8), 238 _FRAME(BIT8), /* auth-data1 */ 515 _FRAME(BIT8), /* type */ 516 _FRAME(BIT8), /* detail */ 527 _FRAME(BIT8), /* sameScreen */ [all …]
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/dports/editors/2bsd-vi/ex-050325/ |
H A D | ex_re.c | 461 #ifdef BIT8 465 #ifdef BIT8 469 #ifdef BIT8 475 #ifdef BIT8 479 #ifdef BIT8 484 #ifdef BIT8 560 #ifdef BIT8 670 #ifdef BIT8 678 #ifdef BIT8 687 #ifdef BIT8 [all …]
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 147 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Exce… 161 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 173 #define INSTS_TSFF BIT8 // Tx Status FIFO full 207 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 214 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 240 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du… 268 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 317 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 147 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Exce… 161 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 173 #define INSTS_TSFF BIT8 // Tx Status FIFO full 207 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 214 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 240 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du… 268 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 317 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 147 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Exce… 161 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 173 #define INSTS_TSFF BIT8 // Tx Status FIFO full 207 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 214 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 240 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du… 268 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 317 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 147 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Exce… 161 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 173 #define INSTS_TSFF BIT8 // Tx Status FIFO full 207 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 214 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 240 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du… 268 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 317 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 154 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Exce… 168 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 180 #define INSTS_TSFF BIT8 // Tx Status FIFO full 214 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 221 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 247 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du… 275 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 324 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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