/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 310 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 203 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 1986 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 3723 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 4439 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerOperation()
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H A D | AArch64SVEInstrInfo.td | 221 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 310 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 203 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 1986 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 3723 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 4439 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerOperation()
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H A D | AArch64SVEInstrInfo.td | 221 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 323 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 205 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 2163 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 4034 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 7151 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerBitreverse()
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H A D | AArch64SVEInstrInfo.td | 225 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 323 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 205 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 2163 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 4034 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 7151 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerBitreverse()
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H A D | AArch64SVEInstrInfo.td | 225 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 323 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 205 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 2163 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 4034 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 7151 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerBitreverse()
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H A D | AArch64SVEInstrInfo.td | 225 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 323 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 205 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 2163 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 4034 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 7151 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerBitreverse()
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H A D | AArch64SVEInstrInfo.td | 225 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 323 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 205 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 2163 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 4034 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 7151 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerBitreverse()
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H A D | AArch64SVEInstrInfo.td | 225 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 323 BITREVERSE_MERGE_PASSTHRU, enumerator
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H A D | AArch64ISelLowering.cpp | 205 case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: in isMergePassthruOpcode() 2190 MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) in getTargetNodeName() 4108 return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl, in LowerINTRINSIC_WO_CHAIN() 7343 return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU, in LowerBitreverse()
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H A D | AArch64SVEInstrInfo.td | 225 def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
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