Home
last modified time | relevance | path

Searched refs:BITS_WMSK (Results 1 – 20 of 20) sorted by relevance

/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c413 BITS_WMSK(0x3fff, 0) | in pm_plls_resume()
414 BITS_WMSK(0x3u, 14)); in pm_plls_resume()
418 ddr_data.clk_sel18 | BITS_WMSK(0x3, 8)); in pm_plls_resume()
422 ddr_data.clk_sel24 | BITS_WMSK(0x7f, 8)); in pm_plls_resume()
426 ddr_data.clk_sel20 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
430 ddr_data.clk_sel1 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
434 ddr_data.clk_sel0 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
486 sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0)); in rk3328_pmic_resume()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c413 BITS_WMSK(0x3fff, 0) | in pm_plls_resume()
414 BITS_WMSK(0x3u, 14)); in pm_plls_resume()
418 ddr_data.clk_sel18 | BITS_WMSK(0x3, 8)); in pm_plls_resume()
422 ddr_data.clk_sel24 | BITS_WMSK(0x7f, 8)); in pm_plls_resume()
426 ddr_data.clk_sel20 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
430 ddr_data.clk_sel1 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
434 ddr_data.clk_sel0 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
486 sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0)); in rk3328_pmic_resume()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c413 BITS_WMSK(0x3fff, 0) | in pm_plls_resume()
414 BITS_WMSK(0x3u, 14)); in pm_plls_resume()
418 ddr_data.clk_sel18 | BITS_WMSK(0x3, 8)); in pm_plls_resume()
422 ddr_data.clk_sel24 | BITS_WMSK(0x7f, 8)); in pm_plls_resume()
426 ddr_data.clk_sel20 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
430 ddr_data.clk_sel1 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
434 ddr_data.clk_sel0 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
486 sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0)); in rk3328_pmic_resume()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c413 BITS_WMSK(0x3fff, 0) | in pm_plls_resume()
414 BITS_WMSK(0x3u, 14)); in pm_plls_resume()
418 ddr_data.clk_sel18 | BITS_WMSK(0x3, 8)); in pm_plls_resume()
422 ddr_data.clk_sel24 | BITS_WMSK(0x7f, 8)); in pm_plls_resume()
426 ddr_data.clk_sel20 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
430 ddr_data.clk_sel1 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
434 ddr_data.clk_sel0 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
486 sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0)); in rk3328_pmic_resume()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c413 BITS_WMSK(0x3fff, 0) | in pm_plls_resume()
414 BITS_WMSK(0x3u, 14)); in pm_plls_resume()
418 ddr_data.clk_sel18 | BITS_WMSK(0x3, 8)); in pm_plls_resume()
422 ddr_data.clk_sel24 | BITS_WMSK(0x7f, 8)); in pm_plls_resume()
426 ddr_data.clk_sel20 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
430 ddr_data.clk_sel1 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
434 ddr_data.clk_sel0 | BITS_WMSK(0x1f, 0)); in pm_plls_resume()
486 sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0)); in rk3328_pmic_resume()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/soc/
H A Dsoc.h12 #ifndef BITS_WMSK
13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/soc/
H A Dsoc.h12 #ifndef BITS_WMSK
13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/soc/
H A Dsoc.h12 #ifndef BITS_WMSK
13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/soc/
H A Dsoc.h12 #ifndef BITS_WMSK
13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/soc/
H A Dsoc.h12 #ifndef BITS_WMSK
13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h20 #ifndef BITS_WMSK
21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h20 #ifndef BITS_WMSK
21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h20 #ifndef BITS_WMSK
21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h20 #ifndef BITS_WMSK
21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h20 #ifndef BITS_WMSK
21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) macro
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c636 ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14)); in pvtm_32k_config_restore()
677 ddr_data.pmugrf_soc_con0 | BITS_WMSK(0x1, 12)); in ddr_sleep_config_restore()
681 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 4)); in ddr_sleep_config_restore()
684 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 5)); in ddr_sleep_config_restore()
688 ddr_data.ddrstdby_con0 | BITS_WMSK(0x1, 0)); in ddr_sleep_config_restore()
692 ddr_data.ddrgrf_con1 | BITS_WMSK(0x1f, 0)); in ddr_sleep_config_restore()
696 ddr_data.ddrc_pwrctrl | BITS_WMSK(0x3, 0)); in ddr_sleep_config_restore()
955 ddr_data.clk_sel0 | BITS_WMSK(0xf, 8)); in pm_plls_resume()
959 ddr_data.clk_sel0 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c636 ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14)); in pvtm_32k_config_restore()
677 ddr_data.pmugrf_soc_con0 | BITS_WMSK(0x1, 12)); in ddr_sleep_config_restore()
681 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 4)); in ddr_sleep_config_restore()
684 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 5)); in ddr_sleep_config_restore()
688 ddr_data.ddrstdby_con0 | BITS_WMSK(0x1, 0)); in ddr_sleep_config_restore()
692 ddr_data.ddrgrf_con1 | BITS_WMSK(0x1f, 0)); in ddr_sleep_config_restore()
696 ddr_data.ddrc_pwrctrl | BITS_WMSK(0x3, 0)); in ddr_sleep_config_restore()
955 ddr_data.clk_sel0 | BITS_WMSK(0xf, 8)); in pm_plls_resume()
959 ddr_data.clk_sel0 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c636 ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14)); in pvtm_32k_config_restore()
677 ddr_data.pmugrf_soc_con0 | BITS_WMSK(0x1, 12)); in ddr_sleep_config_restore()
681 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 4)); in ddr_sleep_config_restore()
684 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 5)); in ddr_sleep_config_restore()
688 ddr_data.ddrstdby_con0 | BITS_WMSK(0x1, 0)); in ddr_sleep_config_restore()
692 ddr_data.ddrgrf_con1 | BITS_WMSK(0x1f, 0)); in ddr_sleep_config_restore()
696 ddr_data.ddrc_pwrctrl | BITS_WMSK(0x3, 0)); in ddr_sleep_config_restore()
955 ddr_data.clk_sel0 | BITS_WMSK(0xf, 8)); in pm_plls_resume()
959 ddr_data.clk_sel0 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c636 ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14)); in pvtm_32k_config_restore()
677 ddr_data.pmugrf_soc_con0 | BITS_WMSK(0x1, 12)); in ddr_sleep_config_restore()
681 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 4)); in ddr_sleep_config_restore()
684 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 5)); in ddr_sleep_config_restore()
688 ddr_data.ddrstdby_con0 | BITS_WMSK(0x1, 0)); in ddr_sleep_config_restore()
692 ddr_data.ddrgrf_con1 | BITS_WMSK(0x1f, 0)); in ddr_sleep_config_restore()
696 ddr_data.ddrc_pwrctrl | BITS_WMSK(0x3, 0)); in ddr_sleep_config_restore()
955 ddr_data.clk_sel0 | BITS_WMSK(0xf, 8)); in pm_plls_resume()
959 ddr_data.clk_sel0 | BITS_WMSK(0xf, 0)); in pm_plls_resume()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c636 ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14)); in pvtm_32k_config_restore()
677 ddr_data.pmugrf_soc_con0 | BITS_WMSK(0x1, 12)); in ddr_sleep_config_restore()
681 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 4)); in ddr_sleep_config_restore()
684 ddr_data.ddrgrf_con0 | BITS_WMSK(0x1, 5)); in ddr_sleep_config_restore()
688 ddr_data.ddrstdby_con0 | BITS_WMSK(0x1, 0)); in ddr_sleep_config_restore()
692 ddr_data.ddrgrf_con1 | BITS_WMSK(0x1f, 0)); in ddr_sleep_config_restore()
696 ddr_data.ddrc_pwrctrl | BITS_WMSK(0x3, 0)); in ddr_sleep_config_restore()
955 ddr_data.clk_sel0 | BITS_WMSK(0xf, 8)); in pm_plls_resume()
959 ddr_data.clk_sel0 | BITS_WMSK(0xf, 0)); in pm_plls_resume()