| /dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 28 #define BM_PLL_ENABLE (0x1 << 13) macro
249 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 29 #define BM_PLL_ENABLE (0x1 << 13) macro
264 pll->enable_bit = BM_PLL_ENABLE; in imx_clk_pllv3()
|