Home
last modified time | relevance | path

Searched refs:BUFGCTRL (Results 1 – 4 of 4) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A DWrapBufg.vhd35 -- lines of the BUFGCTRL will be used. If aCe is synchronous to ClkIn, then the CE pins
67 -- BUFGCTRL is falling edge sensitive and held at Low prior to the input switching.
71 -- IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching
83 -- of the BUFGCTRL since setup and hold times at the S* pins do not have
100 --vhook_i BUFGCTRL GlobalBuffer
114 GlobalBuffer: BUFGCTRL
143 --vscan # are met at the CE pins of the BUFGCTRL (these paths are analyzed by the
146 --vscan *[WrapBufg]GlobalBuffer/[BUFGCTRL]O
150 -- Check that enable lines match up with the generics of the BUFGCTRL
159 & "the BUFGCTRL generic and the SEL line"
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_cap_gen/
H A Dcatcodec_ddr_cmos.v86 …BUFGCTRL BUFGCTRL_radio_clk (.I0(clk0), .I1(clkdv), .S0(~mimo_r), .S1(mimo_r), .CE0(radio_clk_lock…
H A Dcat_io_lvds_dual_mode.v119 BUFGCTRL BUFGCTRL_radio_clk (
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_sim.v114 module BUFGCTRL( module