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/dports/math/gap/gap-4.11.0/pkg/FPLSA-1.2.4/lib/
H A Dserr-b06.in1 Generators B_6:
/dports/science/cp2k/cp2k-2e995eec7fd208c8a72d9544807bd8b8ba8cd1cc/tests/QS/regtest-sym-4/
H A Dc_32_B6Cu.inp15 #B_6 Ca & Pm(-3)m & #221 & cP7 & D2_1
/dports/science/cp2k-data/cp2k-7.1.0/tests/QS/regtest-sym-4/
H A Dc_32_B6Cu.inp15 #B_6 Ca & Pm(-3)m & #221 & cP7 & D2_1
/dports/science/nwchem-data/nwchem-7.0.2-release/src/basis/libraries/
H A D6-311gss_polarization25 basis "B_6-311G** Polarization" SPHERICAL
H A D6-311gs_polarization22 basis "B_6-311G* Polarization" SPHERICAL
H A D6-31gs_polarization22 basis "B_6-31G* Polarization" CARTESIAN
H A D6-31gss_polarization29 basis "B_6-31G** Polarization" CARTESIAN
H A D6-311g2df_2pd99 basis "B_6-311G(2df,2pd)" SPHERICAL
/dports/science/nwchem/nwchem-7b21660b82ebd85ef659f6fba7e1e73433b0bd0a/src/basis/libraries/
H A D6-311gss_polarization25 basis "B_6-311G** Polarization" SPHERICAL
H A D6-311gs_polarization22 basis "B_6-311G* Polarization" SPHERICAL
H A D6-31gs_polarization22 basis "B_6-31G* Polarization" CARTESIAN
H A D6-31gss_polarization29 basis "B_6-31G** Polarization" CARTESIAN
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dcomplex_dot_prod.ll46 ; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2
47 ; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]])
/dports/lang/sdcc/sdcc-4.0.0/device/include/mcs51/
H A Dw7100.h52 SBIT(B_6, 0xF0, 6);

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