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Searched refs:Banks (Results 1 – 25 of 1573) sorted by relevance

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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/
H A Dstm32h7xx_hal_flash_ex.c325 if(pEraseInit->Banks == FLASH_BANK_1) in HAL_FLASHEx_Erase_IT()
343 if(pEraseInit->Banks == FLASH_BANK_1) in HAL_FLASHEx_Erase_IT()
501 if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) in HAL_FLASHEx_OBGetConfig()
754 assert_param(IS_FLASH_BANK(Banks)); in FLASH_MassErase()
818 if((Banks & FLASH_BANK_1) == FLASH_BANK_1) in FLASH_Erase_Sector()
828 if((Banks & FLASH_BANK_2) == FLASH_BANK_2) in FLASH_Erase_Sector()
857 assert_param(IS_FLASH_BANK(Banks)); in FLASH_OB_EnableWRP()
859 if((Banks & FLASH_BANK_1) == FLASH_BANK_1) in FLASH_OB_EnableWRP()
890 assert_param(IS_FLASH_BANK(Banks)); in FLASH_OB_DisableWRP()
1248 assert_param(IS_FLASH_BANK(Banks)); in FLASH_OB_PCROPConfig()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
282 std::vector<RegisterBank> Banks; in run() local
299 Banks.push_back(Bank); in run()
304 for (const auto &Bank : Banks) { in run()
318 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
282 std::vector<RegisterBank> Banks; in run() local
299 Banks.push_back(Bank); in run()
304 for (const auto &Bank : Banks) { in run()
318 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
218 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
242 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
259 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
305 for (const auto &Bank : Banks) { in run()
319 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
218 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
242 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
259 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
305 for (const auto &Bank : Banks) { in run()
319 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp138 for (const auto &Bank : Banks) in emitHeader()
149 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
217 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
222 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
246 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
263 for (const auto &Bank : Banks) in emitBaseClassImplementation()
285 std::vector<RegisterBank> Banks; in run() local
302 Banks.push_back(Bank); in run()
307 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
218 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
242 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
259 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
305 for (const auto &Bank : Banks) { in run()
319 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp136 for (const auto &Bank : Banks) in emitHeader()
147 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
215 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
284 std::vector<RegisterBank> Banks; in run() local
301 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
320 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks) in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
300 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
321 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp135 for (const auto &Bank : Banks)
146 const std::vector<RegisterBank> &Banks) {
214 std::vector<RegisterBank> &Banks) {
219 for (const auto &Bank : Banks) {
243 for (const auto &Bank : Banks) {
260 for (const auto &Bank : Banks)
283 std::vector<RegisterBank> Banks;
300 Banks.push_back(Bank);
306 for (const auto &Bank : Banks) {
321 emitHeader(OS, TargetName, Banks);
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp136 for (const auto &Bank : Banks) in emitHeader()
147 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() argument
215 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() argument
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
284 std::vector<RegisterBank> Banks; in run() local
301 Banks.push_back(Bank); in run()
306 for (const auto &Bank : Banks) { in run()
320 emitHeader(OS, TargetName, Banks); in run()
[all …]
/dports/emulators/nestopia/nestopia-1.51.1/source/core/board/
H A DNstBoardMmc5.cpp68 Mmc5::Banks::Banks(uint wrkSize) in Banks() function in Nes::Core::Boards::Mmc5::Banks
734 ROM_8_A_C = Banks::READABLE_8|Banks::READABLE_A|Banks::READABLE_C, in UpdatePrg()
736 RAM_8_A_C = Banks::WRITABLE_8|Banks::WRITABLE_A|Banks::WRITABLE_C|ROM_8_A_C, in UpdatePrg()
1278 banks.security |= Banks::READABLE_6|Banks::WRITABLE_6;
1283 banks.security &= ~uint(Banks::READABLE_6|Banks::WRITABLE_6);
1463 NST_VERIFY( (banks.security & Banks::CAN_WRITE_6) == Banks::CAN_WRITE_6 );
1465 if ((banks.security & Banks::CAN_WRITE_6) == Banks::CAN_WRITE_6)
1471 NST_VERIFY( (banks.security & Banks::CAN_WRITE_8) == Banks::CAN_WRITE_8 );
1473 if ((banks.security & Banks::CAN_WRITE_8) == Banks::CAN_WRITE_8)
1481 if ((banks.security & Banks::CAN_WRITE_A) == Banks::CAN_WRITE_A) in NES_POKE_AD()
[all …]
/dports/games/libretro-nestopia/nestopia-2b0315c/source/core/board/
H A DNstBoardMmc5.cpp68 Mmc5::Banks::Banks(uint wrkSize) in Banks() function in Nes::Core::Boards::Mmc5::Banks
735 ROM_8_A_C = Banks::READABLE_8|Banks::READABLE_A|Banks::READABLE_C, in UpdatePrg()
737 RAM_8_A_C = Banks::WRITABLE_8|Banks::WRITABLE_A|Banks::WRITABLE_C|ROM_8_A_C, in UpdatePrg()
1279 banks.security |= Banks::READABLE_6|Banks::WRITABLE_6;
1284 banks.security &= ~uint(Banks::READABLE_6|Banks::WRITABLE_6);
1464 NST_VERIFY( (banks.security & Banks::CAN_WRITE_6) == Banks::CAN_WRITE_6 );
1466 if ((banks.security & Banks::CAN_WRITE_6) == Banks::CAN_WRITE_6)
1472 NST_VERIFY( (banks.security & Banks::CAN_WRITE_8) == Banks::CAN_WRITE_8 );
1474 if ((banks.security & Banks::CAN_WRITE_8) == Banks::CAN_WRITE_8)
1482 if ((banks.security & Banks::CAN_WRITE_A) == Banks::CAN_WRITE_A) in NES_POKE_AD()
[all …]
/dports/games/stendhal/stendhal-1.35/src/games/stendhal/server/entity/slot/
H A DBankAccessorManager.java28 private final HashMap<Banks, List<Entity>> accessors;
32 accessors = new HashMap<Banks, List<Entity>>(); in BankAccessorManager()
55 public void add(final Banks bank, final Entity entity) { in add()
70 private List<Entity> getListAddingUnknownBanks(final Banks bank) { in getListAddingUnknownBanks()
86 protected List<Entity> get(final Banks bank) { in get()
H A DBanks.java19 public enum Banks { enum
41 private Banks(final String slotName) { in Banks() method in Banks
60 public static Banks getBySlotName(final String slotName) { in getBySlotName()
61 for (final Banks bank : values()) { in getBySlotName()
/dports/devel/matreshka/matreshka-0.7.0/source/xml/sax/
H A Dxml-sax-pretty_writers.adb383 procedure Merge (Current : in out Mappings.Map; Bank : Banks.Map) is
384 C : Banks.Cursor := Banks.First (Bank);
387 while Banks.Has_Element (C) loop
388 Mappings.Include (Current, Banks.Key (C), Banks.Element (C));
389 Banks.Next (C);
669 Position : Banks.Cursor := Self.Requested_NS.First;
672 while Banks.Has_Element (Position) loop
676 if not Banks.Element (Position).Is_Empty then
680 Self.Destination.Put (Banks.Element (Position));
685 Self.Destination.Put (Banks.Key (Position));
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/dports/databases/cayley/cayley-0.7.5-2-gcf576ba/vendor/github.com/jackc/fake/data/en/
H A Dindustries62 Foreign Money Center Banks
63 Foreign Regional Banks
68 Money Center Banks
80 Regional - Mid-Atlantic Banks
81 Regional - Midwest Banks
82 Regional - Northeast Banks
83 Regional - Pacific Banks
84 Regional - Southeast Banks
85 Regional - Southwest Banks
/dports/games/golly/golly-3.3-src/Patterns/Self-Rep/Banks/
H A DBanks-III-demo.rle1 # Edwin Roger Banks, PhD Thesis 1971
6 # Here Banks shows that his previous 3-state CA can be implemented
8 # and signals operate in a similar fashion to Banks-II.
12 x = 89, y = 54, rule = Banks-III
/dports/finance/aqbanking/aqbanking-6.2.10/src/libs/plugins/bankinfo/generic/
H A DREADME13 German Banks:
22 Austrian Banks:
29 Swiss Banks:
34 US Banks:

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