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Searched refs:CACHE_COHERENCE_PAD_REAL (Results 1 – 16 of 16) sorted by relevance

/dports/science/axom/axom-0.6.1/src/axom/sidre/examples/lulesh2/
H A Dlulesh-comm.cc282 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
292 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
302 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
312 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
322 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
332 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
342 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
352 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
740 cmsg * CACHE_COHERENCE_PAD_REAL] ; in CommSend()
1171 cmsg * CACHE_COHERENCE_PAD_REAL] ; in CommSBN()
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H A Dlulesh_tuple.h120 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
123 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL-1))
H A Dlulesh.h120 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
123 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL-1))
H A Dlulesh-init.cc365 (m_rowMax & m_colMax & m_planeMax)) * CACHE_COHERENCE_PAD_REAL ; in SetupCommBuffers()
711 if (MAX_FIELDS_PER_MPI_COMM > CACHE_COHERENCE_PAD_REAL) { in InitMeshDecomp()
/dports/science/axom/axom-0.6.1/src/axom/slam/examples/lulesh2.0.3/
H A Dlulesh-comm.cpp350 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
361 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
372 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
383 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
1399 cmsg * CACHE_COHERENCE_PAD_REAL]; in CommSBN()
1412 cmsg * CACHE_COHERENCE_PAD_REAL]; in CommSBN()
1426 cmsg * CACHE_COHERENCE_PAD_REAL]; in CommSBN()
1440 cmsg * CACHE_COHERENCE_PAD_REAL]; in CommSBN()
1454 cmsg * CACHE_COHERENCE_PAD_REAL]; in CommSBN()
1468 cmsg * CACHE_COHERENCE_PAD_REAL]; in CommSBN()
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H A Dlulesh_tuple.hpp97 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
100 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL-1))
H A Dlulesh.hpp100 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
103 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL - 1))
H A Dlulesh-init.cpp378 (m_rowMax & m_colMax & m_planeMax)) * CACHE_COHERENCE_PAD_REAL; in SetupCommBuffers()
793 if (MAX_FIELDS_PER_MPI_COMM > CACHE_COHERENCE_PAD_REAL) in InitMeshDecomp()
/dports/science/axom/axom-0.6.1/src/axom/slam/examples/lulesh2.0.3_orig/
H A Dlulesh-comm.cc277 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
287 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
297 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
307 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
317 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
327 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
337 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
347 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
735 cmsg * CACHE_COHERENCE_PAD_REAL] ; in CommSend()
1166 cmsg * CACHE_COHERENCE_PAD_REAL] ; in CommSBN()
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H A Dlulesh_tuple.h101 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
104 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL-1))
H A Dlulesh.h99 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
102 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL - 1))
H A Dlulesh-init.cc372 (m_rowMax & m_colMax & m_planeMax)) * CACHE_COHERENCE_PAD_REAL ; in SetupCommBuffers()
693 if (MAX_FIELDS_PER_MPI_COMM > CACHE_COHERENCE_PAD_REAL) { in InitMeshDecomp()
/dports/science/ascent/ascent-0.7.1-66-gbcf2742a/src/examples/proxies/lulesh2.0.3/
H A Dlulesh-comm.cc277 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
287 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
297 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
307 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
317 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
327 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
337 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
347 cmsg * CACHE_COHERENCE_PAD_REAL], in CommRecv()
735 cmsg * CACHE_COHERENCE_PAD_REAL] ; in CommSend()
1166 cmsg * CACHE_COHERENCE_PAD_REAL] ; in CommSBN()
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H A Dlulesh_tuple.h101 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
104 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL-1))
H A Dlulesh.h105 #define CACHE_COHERENCE_PAD_REAL (128 / sizeof(Real_t)) macro
108 (((n) + (CACHE_COHERENCE_PAD_REAL - 1)) & ~(CACHE_COHERENCE_PAD_REAL-1))
H A Dlulesh-init.cc444 (m_rowMax & m_colMax & m_planeMax)) * CACHE_COHERENCE_PAD_REAL ; in SetupCommBuffers()
763 if (MAX_FIELDS_PER_MPI_COMM > CACHE_COHERENCE_PAD_REAL) { in InitMeshDecomp()