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Searched refs:CACHE_MODE_0 (Results 1 – 25 of 52) sorted by relevance

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/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_suspend.c335 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
381 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | in i915_restore_state()
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm/dist/shared-core/
H A Di915_suspend.c352 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
508 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); in i915_restore_state()
H A Di915_reg.h238 #define CACHE_MODE_0 0x02120 /* 915+ only */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c773 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in gen4_gt_workarounds_init()
782 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); in g4x_gt_workarounds_init()
1981 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in rcs_engine_wa_init()
1990 CACHE_MODE_0, in rcs_engine_wa_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c773 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in gen4_gt_workarounds_init()
782 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); in g4x_gt_workarounds_init()
1981 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in rcs_engine_wa_init()
1990 CACHE_MODE_0, in rcs_engine_wa_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c773 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in gen4_gt_workarounds_init()
782 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); in g4x_gt_workarounds_init()
1981 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in rcs_engine_wa_init()
1990 CACHE_MODE_0, in rcs_engine_wa_init()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/vulkan/
H A DgenX_state.c234 GENX(CACHE_MODE_0), in genX()
H A Dgen8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
/dports/lang/intel-compute-runtime/compute-runtime-21.52.22081/shared/source/aub_mem_dump/
H A Daub_mem_dump_xehp_and_later.inl166 MMIOPair(0x00007000, 0xffff0000), //CACHE_MODE_0
H A Daub_mem_dump_pvc_and_later.inl184 MMIOPair(0x00007000, 0xffff0000), //CACHE_MODE_0
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/vulkan/
H A Dgfx8_cmd_buffer.c69 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/vulkan/
H A Dgfx8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
H A DgenX_state.c245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) { in init_render_queue_state()
/dports/lang/clover/mesa-21.3.6/src/intel/vulkan/
H A DgenX_state.c245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) { in init_render_queue_state()
H A Dgfx8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
/dports/graphics/libosmesa/mesa-21.3.6/src/intel/vulkan/
H A Dgfx8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
H A DgenX_state.c245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) { in init_render_queue_state()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/vulkan/
H A DgenX_state.c245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) { in init_render_queue_state()
H A Dgfx8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/vulkan/
H A DgenX_state.c245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) { in init_render_queue_state()
H A Dgfx8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/vulkan/
H A Dgfx8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
H A DgenX_state.c245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) { in init_render_queue_state()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/vulkan/
H A DgenX_state.c245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) { in init_render_queue_state()
H A Dgfx8_cmd_buffer.c164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()

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