| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 823 clock_enable(CCGR_SDMA2, 0); in set_clk_eqos()
844 clock_enable(CCGR_SDMA2, 1); in set_clk_eqos()
856 clock_enable(CCGR_SDMA2, 0); in imx_eqos_txclk_set_rate()
880 clock_enable(CCGR_SDMA2, 1); in imx_eqos_txclk_set_rate()
|