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Searched refs:CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK (Results 1 – 18 of 18) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c67 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
72 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
H A Dci_baco.c69 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
74 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
H A Dtonga_baco.c67 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
72 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c67 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
72 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
H A Dci_baco.c69 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
74 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
H A Dtonga_baco.c67 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
72 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c67 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
72 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
H A Dci_baco.c69 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
74 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
H A Dtonga_baco.c67 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
72 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_1_sh_mask.h197 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
H A Dsmu_7_1_2_sh_mask.h197 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
H A Dsmu_7_1_3_sh_mask.h223 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_1_sh_mask.h197 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
H A Dsmu_7_1_3_sh_mask.h223 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
H A Dsmu_7_1_2_sh_mask.h197 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_1_sh_mask.h197 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
H A Dsmu_7_1_3_sh_mask.h223 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro
H A Dsmu_7_1_2_sh_mask.h197 #define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 macro