| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
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| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 110 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
127 readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
139 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
213 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
268 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
280 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_basic_init()
404 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
415 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); in cm_get_sdram_clk_hz()
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