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Searched refs:CLKMGR_GEN5_STAT (Results 1 – 25 of 57) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h54 #define CLKMGR_GEN5_STAT 0x14 macro
94 #define CLKMGR_STAT CLKMGR_GEN5_STAT

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