| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 164 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
170 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
172 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
290 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
296 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
323 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
425 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
447 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
452 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
456 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
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