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Searched refs:CLK_TOP_UART0_SEL (Results 1 – 25 of 354) sorted by relevance

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/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt8516.c493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,

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