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/dports/news/cnews/cnews-cr.g_18/readnews/
H A Ddefs.h117 #define CMPN(a, b, n) (*(a) != *(b) ? *(a) - *(b) : strncmp(a, b, n)) macro
H A Dreadnews.c919 } else if (CMPN(hp->h_subject, "Re: ", 4) != 0 && CMPN(hp->h_subject,
/dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/visa/iga/IGALibrary/api/
H A Diga_bxml_ops.hpp39 CMPN = FIRST_OP + 18, enumerator
/dports/devel/shapelib/shapelib-1.5.0/tests/
H A Dstream1.out1281 Field 18: Type=String, Title=`CMPN', Width=30, Decimals=0
1302 CMPN: (NULL)
/dports/lang/clover/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/libosmesa-gallium/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/libosmesa/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/mesa-libs/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/mesa-gallium-va/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/mesa-dri/mesa-21.3.6/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/docs/relnotes/
H A D20.3.5.rst150 - intel/compiler: Enable the ability to emit CMPN instructions
151 - intel/compiler: Make the CMPN builder work like the CMP builder
152 - intel/compiler: Use CMPN for min / max on Gen4 and Gen5
/dports/x11-fm/wcmcommander/WCMCommander-release-0.20.0/src/swl/
H A Dswl_wincore.cpp2031 enum {CMPN = 4}; enumerator
2032 unsigned char cmpLev[CMPN];
2038 while ( i < CMPN && cmpLev[i] == a->cmpLev[i] ) { i++; } in Cmp()
2040 return ( i >= CMPN ) ? 0 : cmpLev[i] < a->cmpLev[i] ? -1 : 1; in Cmp()
2057 UiSelector(): item( 0 ) { for ( int i = 0; i < CMPN; i++ ) { cmpLev[i] = 0; } } in UiSelector()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/lang/clover/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/
H A Dbrw_vec4_builder.h476 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, in CMPN() function
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/
H A Dbrw_vec4_builder.h406 ALU2(CMPN) in ALU2_ACC()

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