| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 70 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 macro
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|