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Searched refs:CP0C0_M (Results 1 – 25 of 31) sorted by relevance

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/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
H A Dcpu.h387 #define CP0C0_M 31
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
H A Dcpu.h387 #define CP0C0_M 31 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dcpu.h391 #define CP0C0_M 31 macro
H A Dtranslate_init.inc.c25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
H A Dkvm.c380 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dcpu.h832 #define CP0C0_M 31 macro
H A Dtranslate_init.inc.c25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
H A Dkvm.c386 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dcpu.h834 #define CP0C0_M 31 macro
H A Dkvm.c403 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dcpu.h832 #define CP0C0_M 31 macro
H A Dtranslate_init.inc.c25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
H A Dkvm.c386 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dcpu.h832 #define CP0C0_M 31 macro
H A Dtranslate_init.inc.c25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
H A Dkvm.c386 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu.h838 #define CP0C0_M 31
H A Dkvm.c397 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu.h838 #define CP0C0_M 31 macro
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dcpu.h838 #define CP0C0_M 31 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dcpu.h933 #define CP0C0_M 31 macro
H A Dtranslate_init.inc.c25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
H A Dkvm.c386 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)

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