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Searched refs:CP0C0_MM (Results 1 – 20 of 20) sorted by relevance

/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dtranslate_init.inc.c376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h836 #define CP0C0_MM 18 macro
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dtranslate_init.inc.c376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h836 #define CP0C0_MM 18 macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dtranslate_init.inc.c376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h836 #define CP0C0_MM 18 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dtranslate_init.inc.c376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h395 #define CP0C0_MM 18 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dtranslate_init.inc.c376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h937 #define CP0C0_MM 18 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu-defs.c.inc376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
456 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h842 #define CP0C0_MM 18
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu-defs.c.inc375 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h842 #define CP0C0_MM 18 macro
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dcpu-defs.c.inc376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
456 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h842 #define CP0C0_MM 18 macro
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dtranslate_init.c.inc376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
456 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
H A Dcpu.h838 #define CP0C0_MM 18 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dcpu.h391 #define CP0C0_MM 17 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dcpu.h391 #define CP0C0_MM 17