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Searched refs:CP0C5_VP (Results 1 – 25 of 45) sorted by relevance

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/dports/emulators/qemu/qemu-6.2.0/hw/mips/
H A Dcps.c61 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); in cpu_mips_itu_supported()
/dports/emulators/qemu60/qemu-6.0.0/hw/mips/
H A Dcps.c61 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); in cpu_mips_itu_supported()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/mips/
H A Dcps.c57 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || in cpu_mips_itu_supported()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/mips/
H A Dcps.c61 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); in cpu_mips_itu_supported()
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dcpu.c88 if (env->CP0_Config5 & (1 << CP0C5_VP)) { in mips_cpu_has_work()
H A Dtranslate_init.inc.c700 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
740 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
H A Dcpu.h935 #define CP0C5_VP 7 macro
/dports/emulators/qemu42/qemu-4.2.1/hw/mips/
H A Dcps.c62 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || in cpu_mips_itu_supported()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dcpu.c88 if (env->CP0_Config5 & (1 << CP0C5_VP)) { in mips_cpu_has_work()
H A Dtranslate_init.inc.c700 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
740 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
/dports/emulators/qemu-utils/qemu-4.2.1/hw/mips/
H A Dcps.c62 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || in cpu_mips_itu_supported()
/dports/emulators/qemu5/qemu-5.2.0/hw/mips/
H A Dcps.c61 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || in cpu_mips_itu_supported()
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dcpu.c88 if (env->CP0_Config5 & (1 << CP0C5_VP)) { in mips_cpu_has_work()
H A Dtranslate_init.inc.c700 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
740 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dcpu.c84 if (env->CP0_Config5 & (1 << CP0C5_VP)) { in mips_cpu_has_work()
H A Dcpu.h494 #define CP0C5_VP 7 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/mips/
H A Dcps.c62 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || in cpu_mips_itu_supported()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/mips/
H A Dcps.c62 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || in cpu_mips_itu_supported()
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dcpu.c91 if (env->CP0_Config5 & (1 << CP0C5_VP)) { in mips_cpu_has_work()
H A Dtranslate_init.c.inc701 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
741 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dcpu.c93 if (env->CP0_Config5 & (1 << CP0C5_VP)) { in mips_cpu_has_work()
H A Dtranslate_init.inc.c817 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
857 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu-defs.c.inc703 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
743 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu-defs.c.inc702 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
742 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dcpu-defs.c.inc703 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
743 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |

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